Euro-Par 2015: Parallel Processing

Abstract

Abstract. In multicore architectures, deciding where to execute the threads of parallel applications is increasingly a significant challenge. This thread mapping has a large impact on the application's performance and energy consumption. Recent research in this area mostly focuses on improving the locality of memory accesses and optimizing the use of shared caches by mapping threads that frequently communicate with each other to processing units that are closer to each other in the memory hierarchy. However, locality-based policies can lead to a substantial performance reduction in some cases due to communication imbalance. In this paper, we perform a comprehensive exploration of communicationaware thread mapping policies in multicore architectures. We develop a set of metrics to evaluate the communication behavior of parallel applications, and describe how these metrics can be used to favor locality-based or balance-based mapping policies. Based on these metrics, we introduce a novel mapping policy that combines locality and balance aspects and achieves the highest overall improvements. We provide an experimental evaluation of the performance gains using different mapping policies as well as a detailed analysis of the sources of energy savings.

Towards the Implementation of a New Multigrid Solver in the DNS Code FS3D for Simulations of Shear-Thinning Jet Break-Up at Higher Reynolds Numbers

“…For further details regarding pcl and the features of UG4 the reader is referred to Vogel et al [38] or Reiter et al [27]. Scalability and parallel performance of UG4 was tested extensively [39]. For integration into FS3D the parallel hierarchical multigrid solver of UG4 is of principal interest.…”

“…On finer grid levels, however, the major amount of overall runtime is required. Nevertheless, a good computation vs. communication ratio is achieved by means of sophisticated parallel smoothing, prolongation and restriction operations [39].…”