Eunomia: Scaling Concurrent Index Structures Under Contention Using HTM

Zhang, Weihua; Wang, Xin; Ji, Shiyu; Wei, Ziyun; Wang, Zhaoguo; Chen, Haibo

doi:10.1109/tpds.2017.2729551

Cited by 4 publications

(1 citation statement)

References 41 publications

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“…Concurrent data structures are fundamental building blocks for computer science. Data layout for better spatial locality and concurrency is becoming ever more crucial in the multiand many-core era [6,10,15,22,34,36,43,53,61,68,69]. Im and Yelick presented a register blocking method to improve the performance of SpMV [17].…”

Section: Related Workmentioning

confidence: 99%

swSpTRSV

Wang

Liu

Xue

et al. 2018

Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

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Sparse triangular solve (SpTRSV) is one of the most important kernels in many real-world applications. Currently, much research on parallel SpTRSV focuses on level-set construction for reducing the number of inter-level synchronizations. However, the out-of-control data reuse and high cost for global memory or shared cache access in inter-level synchronization have been largely neglected in existing work. In this paper, we propose a novel data layout called Sparse Level Tile to make all data reuse under control, and design a Producer-Consumer pairing method to make any inter-level synchronization only happen in very fast register communication. We implement our data layout and algorithms on an SW26010 many-core processor, which is the main buildingblock of the current world fastest supercomputer Sunway Taihulight. The experimental results of testing all 2057 square matrices from the Florida Matrix Collection show that our method achieves an average speedup of 6.9 and the best speedup of 38.5 over parallel level-set method. Our method also outperforms the latest methods on a KNC many-core processor in 1856 matrices and the latest methods on a K80 GPU in 1672 matrices, respectively.

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