Etching titanium nitride gate stacked on high-κ dielectric

Gerharz, J.; Padmaraju, Kishore; Moers, J.; Grützmacher, Detlev

doi:10.1016/j.mee.2011.02.049

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…For CMOS devices with TiN-based electrodes, TiN wet etch process is needed for both gate first and gate last process. Despite several reports of TiN wet etch on high-k gate dielectric to accomplish dual metal gated CMOS integration, [15][16][17] there are few systematic reports about wet chemicals, dielectric types, and post etch anneal on high-k surface. Since high-k dielectric is exposed to wet chemicals and metallic element like residual Ti atom during process would be absorbable to high-k surface, it is of great concern on degraded electrical properties such as higher leakage current caused metallic impurities.…”

Section: Introductionmentioning

confidence: 99%

A Study of Sputtered TiN Gate Electrode Etching with Various Wet Chemicals and Post Etch Annealing for Complementary Metal–Oxide–Semiconductor Device Integration Applications

Heo

Yoo

Choi

et al. 2012

Jpn. J. Appl. Phys.

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Wet chemicals for etching sputtered TiN metal gate and post etch annealing on HfO2 and HfSiON gate dielectrics were studied with metal–oxide–semiconductor devices. Various wet solutions such as SC1 (NH4/H2O2/H2O= 1:2:5), SPM (H2SO4/H2O2= 10:1), and H2O2 were employed to etch the sputtered TiN. Difference in equivalent oxide thickness (EOT) is negligible among etchants while the lowest leakage current density (J g) is attained with only SPM solution. Even though SPM treatment shows relative poor surface morphologies compared to H2O2 process, difference in J g is mainly affected by the amount of absorbed Ti into high-k gate dielectrics during wet etch process. Lower J g using SPM is attributable to the reduced amount of Ti-adsorption due to additional H2SO4 acid in wet chemical solution, which is confirmed by total reflection X-ray fluorescence. Post etch annealing on high-k layer improves film qualities such as suppressed defects – less frequency dependence – and lowers J g further while EOT is slightly increased by about 0.2 nm due to SiO2 interfacial regrowth. HfSiON gate dielectric shows stronger immunity against TiN wet etch compared with HfO2. Thus, appropriate etchant and post annealing for the selective TiN etching are carefully considered to suppress defects and J g for attaining complementary metal–oxide–semiconductor (CMOS) device.

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Section: Introductionmentioning

confidence: 99%