ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms

Sharma, Yanshul; Chakraborty, Shounak; Moulik, Sanjay

doi:10.1007/s11227-021-04257-7

Cited by 25 publications

(6 citation statements)

References 32 publications

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“…where (12) ensures that a task τ i is executed with one V/F core level (v p,k , f p,k ), and (13) restricts that the message of edge e i,j is transmitted with one V/F link level (v l,g , f l,g ).…”

Section: B Problem Formulationmentioning

confidence: 99%

“…To achieve an effective system, appropriate task mapping methods are needed. Most energy-aware task mapping methods in bus-based MPSoCs mainly focus on the energy consumption of computation, e.g., [10]- [12]. To reduce both computation and communication energy consumption, the NoCbased MPSoCs are enhanced with Dynamic Voltage and Frequency Scheduling (DVFS) for cores, routers, and links [13]- [16].…”

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confidence: 99%

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Contention and Reliability-Aware Energy Efficiency Task Mapping on NoC-Based MPSoCs

Mo,

Li,

Kritikakou

et al. 2024

IEEE Trans. Rel.

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Recently, Network-on-Chip (NoC)-based Multi-Processor System-on-Chips (MPSoCs) have become popular computing platforms for real-time applications due to high communication performance and energy efficiency over traditional bus-based MPSoCs. Due to the nature of network structures, network congestion along with transient faults, can significantly affect communication efficiency and system reliability. Most existing works have rarely focused on the concurrent optimization of network contention, reliability, and energy consumption. Here, we study the problem of contention and reliability-aware task mapping under real-time constraints for dynamic voltage and frequency scaling-enabled NoC. The problem entails optimizing voltage/frequency on cores and links to reduce energy consumption and ensure system reliability, while task mapping and slack time are adopted to alleviate network contention and reduce latency. We aim to minimize computation and communication energy and balance workload. This problem is formulated as a mixed-integer nonlinear programming, and we present an effective linearization scheme that equivalently transforms it into a mixed-integer linear programming to find the optimal solution. To reduce computation time, we propose a three-step heuristic, including task allocation, frequency scaling and edge scheduling, and communication contention management. Finally, we perform extensive simulations to evaluate the proposed method. The results show we can achieve 31.6% and 21.7% energy savings, with 95.5% and 98.6% less contention than the existing methods.

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Section: B Problem Formulationmentioning

confidence: 99%

mentioning

confidence: 99%

Contention and Reliability-Aware Energy Efficiency Task Mapping on NoC-Based MPSoCs

Mo,

Li,

Kritikakou

et al. 2024

IEEE Trans. Rel.

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show abstract

“…Sharma et al introduced a heuristic method called ETA-HP designed to optimize energy and temperature efficiency when scheduling real-time periodic tasks on a heterogeneous multicore system with DVFS capability. This technique consists of four stages: Deadline Partitioning, Task-to-Core Allocation, Temperature-Aware Scheduling, and Energy-Aware Scheduling [32]. Moulik et al developed a heuristic approach, called CEAT for scheduling real-time periodic tasks on a heterogeneous multicore platform with DVFS support, focusing on energy efficiency.…”

Section: Related Workmentioning

confidence: 99%

Energy-Aware Successor Tree Consistent EDF Scheduling for PCTGs on MPSoCs

Tariq,

Ali,

Nadeem

et al. 2024

IEEE Access

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Multiprocessor System-on-Chips (MPSoCs) computing architectures are gaining popularity due to their high-performance capabilities and exceptional Quality-of-Service (QoS), making them a particularly wellsuited computing platform for computationally intensive workloads and applications. Nonetheless, The scheduling and allocation of a single task set with precedence restrictions on MPSoCs have presented a persistent research challenge in acquiring energy-efficient solutions. The complexity of this scheduling problem escalates when subject to conditional precedence constraints between the tasks, creating what is known as a Conditional Task Graph (CTG). Scheduling sets of Periodic Conditional Task Graphs (PCTGs) on MPSoC platforms poses even more challenges. This paper focuses on tackling the scheduling challenge for a group of PCTGs on MPSoCs equipped with shared memory. The primary goal is to minimize the overall anticipated energy usage, considering two distinct power models: dynamic and static power models. To address this challenge, this paper introduces an innovative scheduling method named Energy Efficient Successor Tree Consistent Earliest Deadline First (EESEDF). The EESEDF approach is primarily designed to maximize the worst-case processor utilization. Once the tasks are assigned to processors, it leverages the earliest successor tree consistent deadline-first strategy to arrange tasks on each processor. To minimize the overall expected energy consumption, EESEDF solves a convex Non-Linear Program (NLP) to determine the optimal speed for each task. Additionally, the paper presents a highly efficient online Dynamic Voltage Scaling (DVS) heuristic, which operates in O(1) time complexity and dynamically adjusts the task speeds in real-time. We achieved the average improvement, maximum improvement, and minimum improvement of EESEDF+Online-DVS 15%, 17%, and 12%, respectively compared to EESEDF alone. Furthermore, in the second set of experiments, we compared EESEDF against state-of-the-art techniques LESA and NCM. The results showed that EESEDF+Online-DVS outperformed these existing approaches, achieving notable energy efficiency improvements of 25% and 20% over LESA and NCM, respectively. Our proposed scheduler, EESEDF+Online-DVS, also achieves significant energy efficiency gains compared to existing methods. It outperforms IOETCS-Heuristic by approximately 13% while surpassing BESS and CAP-Online by impressive margins of 25% and 35%, respectively.

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“…It also helps to ensure that data is processed in a timely manner and that there are no delays in the data processing pipeline. Thus, the work in [ 24 ] presents a technique for efficient scheduling of real-time tasks on multicore systems, saving energy and reducing temperature by 2.52% and 9.59 C compared to existing methods. Analogously, RESET [ 25 ] improves resource utilization, reduces energy consumption and core temperature.…”

Section: Related Workmentioning

confidence: 99%

A new Apache Spark-based framework for big data streaming forecasting in IoT networks

et al. 2023

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ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms

Cited by 25 publications

References 32 publications

Contention and Reliability-Aware Energy Efficiency Task Mapping on NoC-Based MPSoCs

Contention and Reliability-Aware Energy Efficiency Task Mapping on NoC-Based MPSoCs

Energy-Aware Successor Tree Consistent EDF Scheduling for PCTGs on MPSoCs

A new Apache Spark-based framework for big data streaming forecasting in IoT networks

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