Estimation of Wirebonded Package Inductance and Resistance using Statistical DOE/RSM

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

“…However, existing packaging for commercial SiC MOSFETs is based on wirebonding packaging methods [6] that are typically developed for Si-semiconductor power devices, including both discrete transistor outline (TO) packages for the single die and a power module represented by parts stacking for multi-dies. The parasitic inductance of up to 10 nH was induced by the bonding wire [7], [8]. Because of the high di/dt in the high-frequency switching process, the voltage overshoot and voltage oscillation resulting from high parasitic inductance can cause an increasing electric energy loss, electromagnetic interference, and thermal breakdown of the die [9], [10].…”