Estimation of Topographic Defects Dimensions of Semiconductor Silicon Structures

Abstract

The effect of non-flatness of semiconductor wafers on characteristics of manufactured devices is shown through defocusing of an image of a topological layout of a structure being formed and through reduction of resolution at photolithographic processing. For quality control of non-flatness the Makyoh method is widely used. However, it does not allow obtaining quantitative characteristics of observed defects, which essentially restricts its application. The objective of this work has been developing of a calculation method for dimensions of topographic defects of wafers having semiconductor structures formed on them, which has allowed determining acceptability criteria for wafers, depending on defects dimensions and conducting their timely penalization.A calculation method under development is based on deduction of relationships linking distortion of image elements to curvature of local sections of a semiconductor wafer that has formed structures. These structures have been considered to be image finite elements and within this range the curvature radius has been assumed to be constant. Sequential calculation of deviation of element ends from ideal plane based on determining their curvature radius has allowed obtaining geometry of a target surface in a set range of elements. Conditions of image formation and requirements to structures have been determined.Analytical expressions relating a deviation value of elements of a light-to-dark image with surface geometry have been obtained. This allows conducting effective quantitative control of observed topographic defects both under production and research conditions. Examples of calculation of topographic defects of semiconductor silicon wafers have been provided. Comparison of the obtained results with the data obtained by conventional methods has shown their complete conformity.