Estimation of test metrics for multiple analogue parametric deviations

Bounceur, Ahcène; Mir, Salvador; Simeu, Emmanuel; Rolindez, L.

doi:10.1109/dtis.2006.1708706

Cited by 2 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Section 4 will describe A Tool for Analog/RF BIST Evaluation Using Statistical Models 31:3 these density estimation techniques. From the CDF, it is possible to estimate the test metrics using a direct calculation [Beznia et al 2013b] or via the generation of a larger sample of circuit instances by sampling the CDF model [Bounceur et al 2006]. It must also be noted that an analysis of the CDF model may result in the identification of output parameters that are redundant or that do not contribute to the actual test metrics results.…”

Section: Methodological Flow For Model Selectionmentioning

confidence: 99%

“…The multivariate Gaussian assumption can be validated by computing the correlation coefficients for different standard deviations during a Monte Carlo simulation or by running a multivariate goodness-of-fit test [Fan 1997], or especially a multivariate Gaussian goodness-of-fit test [ Baringhaus and Henze 1988]. As an example, in Bounceur et al [2006] an operational amplifier with 12 performances and two test measures is used where the obtained distribution is a multivariate Gaussian.…”

Section: The Multivariate Gaussian Modelmentioning

confidence: 99%

See 1 more Smart Citation

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Beznia

Bounceur

Euler

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques. . 2015. A tool for analog/RF BIST evaluation using statistical models of circuit parameters.

show abstract

Section: Methodological Flow For Model Selectionmentioning

confidence: 99%

Section: The Multivariate Gaussian Modelmentioning

confidence: 99%

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Beznia

Bounceur

Euler

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…Test metrics will be calculated in future works, following the approach described in 6 . Fault coverage for each performance or test measure is plotted as a function of its limits (specifications in the case of a performance and test criteria in the case of a test measure).…”

Section: Methodsmentioning

confidence: 99%

Test measures evaluation for VCO and charge pump blocks in RF PLLs

2007

View full text Add to dashboard Cite

This work deals with the development of test techniques for RF (Radio Frequency) components. The optimization of production tests for RF PLLs (Phase Locked Loops) is targeted in particular. With devices of ever increasing speed, it is no longer possible to measure some of the classical circuit performances even with dedicated RF testers. This problem has been tackled in recent years by using BIST (Built-In Self Test) techniques for PLLs able to perform on-chip high resolution measurements such as picosecond jitter. However, this risks to become also impossible at very high frequencies.This paper will present some preliminary work towards the optimization of production tests for RF PLLs with the aim of avoiding traditional test measurements such as phase noise. Attention will be focused on single relevant blocks of the RF PLL that have the greatest impact on phase noise and other critical performances. The VCO (Voltage Controlled Oscillator) block will be first studied, since it gives the greatest contribution to phase noise. Our work will proceed by taking into consideration the possibility to detect mismatches and leakages in CP (Charge Pump) currents that cause spurious in the output spectrum. Simulation results in this paper will consider only catastrophic faults in circuit components. The fault coverage of performances and simple test measurements that can be implemented on-chip for the VCO is thus evaluated.

show abstract

Estimation of test metrics for multiple analogue parametric deviations

Cited by 2 publications

References 4 publications

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Test measures evaluation for VCO and charge pump blocks in RF PLLs

Contact Info

Product

Resources

About