Estimation of fixed charge densities in hafnium-silicate gate dielectrics

Kaushik, V.; O’Sullivan, Barry; Pourtois, Geoffrey; Hoornick, N. Van; Delabie, Annelies; Elshocht, Sven Van; Deweerd, W.; Schram, T.; Pantisano, L.; Röhr, E.; Ragnarsson, Lars‐Åke; Gendt, Stefan De; Heyns, Marc

doi:10.1109/ted.2006.882412

Cited by 70 publications

(56 citation statements)

References 10 publications

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“…Moreover, the dependence of V FB on EOT reveals that the fixed oxide charge is mainly distributed either at the Si͑100͒/IL or at the IL/high-interface. 16 This hypothesis is consistent with the tendency of the OV to segregate at the Si/ HfO 2 interface. 17 The EOT is extracted by fitting the C-V curves at 100 kHz including quantum mechanical corrections ͑Fig.…”

supporting

confidence: 81%

Dielectric properties of Er−doped HfO2 (Er∼15%) grown by atomic layer deposition for high-κ gate stacks

Wiemer¹,

Lamagna²,

Baldovino

et al. 2010

Applied Physics Letters

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Er − doped HfO2 (Er∼15%) films are grown by atomic layer deposition on Si(100). The characteristics of the doped oxide are compared with those of HfO2. In Er−doped HfO2, the stabilization of the cubic structure, together with the effect of the high polarizability of Er3+, allow to obtain a dielectric constant of ∼33 after annealing at 900 °C. The insertion of Er within the metallic sublattice of HfO2 reduces the net density of fixed charges, due to the creation of oxygen vacancies. For similar equivalent oxide thickness, lower leakage currents are measured for Er−doped HfO2 than for HfO2.

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supporting

confidence: 81%

Dielectric properties of Er−doped HfO2 (Er∼15%) grown by atomic layer deposition for high-κ gate stacks

Wiemer¹,

Lamagna²,

Baldovino

et al. 2010

Applied Physics Letters

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“…This low bulk charge density is in line with the expectations for SiO 2 films prepared by ALD and PECVD after annealing. 57 It indicates that the films have a low density of bulk defect states. Nevertheless, the obtained bulk charge density is equivalent to a surface charge density of $3.5 Â 10 11 cm À2 for a film of 150 nm, which explains the observed increase of Q eff in Fig.…”

Section: B Interpretation Of the Modeling Resultsmentioning

confidence: 99%

Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation

Terlinden

Dingemans

Vandalon

et al. 2014

Journal of Applied Physics

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By accurately tuning the SiO2 interlayer thickness the density and polarity of charges in Si/SiO2/Al2O3 stacks can be controlled. We report on the number density, polarity, and physical location of charges present in the stacks as studied by optical second-harmonic generation (SHG). Depending on the SiO2 interlayer thickness (1–150 nm) the effective charge density in the Si/SiO2/Al2O3 stacks ranges from 1013 to 1011 cm−2 for both n- and p-type silicon. The polarity of the charges switches from negative to positive around a SiO2 interlayer thickness of 5–10 nm at which point the effective charge density in the stacks is negligible. This switch in polarity is apparent from spectroscopic, time-dependent, and azimuthal SHG measurements. The observed trends in charge density and polarity can be explained by tunneling of electrons into defect states at the SiO2/Al2O3 interface as well as the presence of fixed and bulk charges at the Si/SiO2 interface and in the SiO2, respectively. This charge mechanism appears to hold generally for Si/SiO2/Al2O3 stacks as similar results were observed for SiO2 films prepared by various techniques.

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“…moving forward. This group includes patterning proximity effects (both classical, and optical proximity correction (OPC, [4]), line-edge and line-width roughness (LER and LWR, respectively [5]), polish variations (shallow trench isolation, STI [6], and gate [7]), and variations in the gate dielectric (oxide thickness variations [8], fixed charge [9], and defects and traps [10]). A large variety of mitigation strategies exist for these historical sources [3,4,7,11], ranging from strategic improvements (for example, restricted design rules as in Figure 4, or optimized cell designs as in Figure 1) to tactical improvements (for example, resist and anneal improvements such as illustrated in Figure 3).…”

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confidence: 99%

Variability in nanoscale CMOS technology

Kuhn

2011

Sci. China Inf. Sci.

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Moore's Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation. This paper discusses the importance of process variation in modern CMOS transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques (including circuit and SRAM data from the 32 nm node), and compares recent intrinsic transistor variation performance from the literature.

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Estimation of fixed charge densities in hafnium-silicate gate dielectrics

Cited by 70 publications

References 10 publications

Dielectric properties of Er−doped HfO2 (Er∼15%) grown by atomic layer deposition for high-κ gate stacks

Dielectric properties of Er−doped HfO2 (Er∼15%) grown by atomic layer deposition for high-κ gate stacks

Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation

Variability in nanoscale CMOS technology

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