Establishment of Light Weight Cryptography for Resource Constraint Environment Using FPGA

Baskar, Chanthini

doi:10.1016/j.procs.2016.02.027

Cited by 27 publications

(12 citation statements)

References 8 publications

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“…The proposed ID-XT-EA-LFSR algorithm has improved the performance of FPGA on LP-Virtex-6 device by 21.27 % of LUT, 76.92% of flip-flop and 53.125% of slice compared to the QTL algorithm [16]. From the Table 1, it is clear that the number of LUT, flip-flop and slices are reduced and the operating frequency has increased compared to the existing algorithms such as QTL [16], DROM-CSLA-QTL [17], and XTEA [18]. The key management is an important task in a cryptosystem.…”

Section: Resultsmentioning

confidence: 97%

“…The chaotic map based key is used for encryption and decryption process. It is not suitable for high data rate process [18]. So, in ID-XT-EA-LFSR algorithm, key generation portion of an algorithm must be designed carefully in order to ensure the security of the system.…”

Section: Resultsmentioning

confidence: 99%

“…The Dual Port Read Only Memory-Carry Select Adder based QTL method is introduced to reduce computation complexity and hardware usage for image encryption and decryption process [17]. A light weight cryptographic with a chaotic map based key generation scheme is proposed for efficient security purpose [18]. Compared to these methods the proposed ID-XT-EA-LFSR algorithm provides better security performances.…”

Section: Literature Surveymentioning

confidence: 99%

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VLSI Implementation of Hybrid Cryptography Algorithm Using LFSR Key

Acholli¹,

Ningappa²

2019

IJIES

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The security and confidentiality of the information has become a significant factor in the communication field. Several techniques for encryption and decryption are proposed to promote the security of the communication systems. Most powerful and significant part of the encryption is a key generation. Presently, hackers are able to break the key with help of the modern high computing machines. In this research, hybrid cryptographic algorithm -Extended Tiny Encryption Algorithm (XTEA) combined with International Data Encryption Algorithm (IDEA) was implemented for improving the security in real-time applications. A large key size ensures the randomness, but proportionally maximizes the network load with high complexity. To overcome this problem, the random numbers were generated using a Linear Feedback Shift Register (LFSR) scheme for key function. This algorithm was appropriate for encryption and decryption of online streaming data. The proposed method is named as International Data -Extended Tiny based Encryption Algorithm -LFSR (ID-XT-EA-LFSR) method. The ID-XT-EA-LFSR method improves the FPGA performances up to 50.43% compared to the QTL, DROM-CSLA-QTL and XTEA algorithms.

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Section: Resultsmentioning

confidence: 97%

Section: Resultsmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

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VLSI Implementation of Hybrid Cryptography Algorithm Using LFSR Key

Acholli¹,

Ningappa²

2019

IJIES

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“…A user authentication and key agreement scheme also based on XOR computations was proposed in [52] and then improved by [53], which enables a remote user to securely negotiate a session key with an IoT device, using a lean key agreement protocol. Baskar et al recently proposed a lightweight encryption algorithm that uses a chaos map-based key [54], which was also implemented on a Field Programmable Gate Array (FPGA), Its performance is also compared with other lightweight algorithms in the literature. The algorithm is capable of achieving maximum throughput of 200 kbit/s on an FPGA with 1550 logic gates and 128 bit of key size.…”

Section: A Iot Device Identification and Authenticationmentioning

confidence: 99%

Securing the Internet of Things in the Age of Machine Learning and Software-Defined Networking

Restuccia

D’Oro

Melodia

2018

IEEE Internet Things J.

224

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The Internet of Things (IoT) realizes a vision where billions of interconnected devices are deployed just about everywhere, from inside our bodies to the most remote areas of the globe. As the IoT will soon pervade every aspect of our lives and will be accessible from anywhere, addressing critical IoT security threats is now more important than ever. Traditional approaches where security is applied as an afterthought and as a "patch" against known attacks are insufficient. Indeed, nextgeneration IoT challenges will require a new secure-by-design vision, where threats are addressed proactively and IoT devices learn to dynamically adapt to different threats. To this end, machine learning and software-defined networking will be key to provide both reconfigurability and intelligence to the IoT devices. In this paper, we first provide a taxonomy and survey the state of the art in IoT security research, and offer a roadmap of concrete research challenges related to the application of machine learning and software-defined networking to address existing and nextgeneration IoT security threats.

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“…Key generation module of the cryptographic algorithm should be designed more careful in order to ensure the security of any system and it consumes several computational steps for strong key without correlation with further generated key value. The powerful algorithm is necessary to increase the encryption key randomness [9].…”

mentioning

confidence: 99%

Lorentz Chaotic System key generation with Low Area FPGA Implementation using Present Security Algorithm

Parikibandla¹,

Sreenivas²

2019

IJRTE

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Recently, the study of lightweight symmetric ciphers has gained more importance because of high requirement in the services for security in the CCNs (Constrained Computing Environments): Wireless Sensor Network (WSN), Internet of Things (IoT). A lightweight cipher is a cryptographic algorithm which is used for low resource device, minimal area optimization, low power design and attains sufficient security level. Size of the key is considered as major challenges in the cryptographic algorithms, because it increases the complexity of the cryptographic algorithm. To overcome this issue and improve the security, Lorentz Chaotic System (LCS) based PRESENT architecture is introduced in this research. The PRESENT lightweight block cipher is selected due to it is most general and famous lightweight algorithms. Hence, the random numbers were generated for a key purpose by using an LCS circuit. The streaming data will be encrypt and decrypt by using this algorithm. In this research, the modified lightweight block cipher algorithm is called as LCS-PRESENT architecture. Finally, the performance of LCS -PRESENT architecture was evaluated by FPGA hardware utilizations such as Lookup Table (LUT), flip flop, slices, and frequency. The security level of LCS-PRESENT architecture was analysed based on encrypted and decrypted results in XILINX tool. The LCS-PRESENT architecture utilizes the FPGA device to attain maximum accuracy and throughput, such as 30 of LUTs, 115 of flip flops and 47 of slices from available sources compared to existing cryptographic algorithms.

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Establishment of Light Weight Cryptography for Resource Constraint Environment Using FPGA

Cited by 27 publications

References 8 publications

VLSI Implementation of Hybrid Cryptography Algorithm Using LFSR Key

VLSI Implementation of Hybrid Cryptography Algorithm Using LFSR Key

Securing the Internet of Things in the Age of Machine Learning and Software-Defined Networking

Lorentz Chaotic System key generation with Low Area FPGA Implementation using Present Security Algorithm

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