Escape routing of differential pairs considering length matching

Li, Tai-Hung; Chen, Wanchun; Cai, Xian-Ting; Chen, Tai-Chen

doi:10.1109/aspdac.2012.6164934

Cited by 9 publications

(2 citation statements)

References 22 publications

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“…Yan et al [20] proposed a negotiation-based routing algorithm considering routing congestion to achieve routing for differential pairs. Li et al [22] employed a two-stage scheme and a minimum-cost maximum-flow algorithm to simultaneously route all differential pairs. Wang and Jiao et al [23], [24] developed unordered and ordered escape routing algorithms for staggered pin arrays, taking into consideration the constraints of differential pairs.…”

Section: A Escape Routing and Region Routingmentioning

confidence: 99%

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing. INDEX TERMS physical design, printed circuit board, routing, Machine learning I. INTRODUCTION 1 This article has been accepted for publication in IEEE Access.

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Section: A Escape Routing and Region Routingmentioning

confidence: 99%

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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“…Sato et al [15] presented a pattern generator for set-pair routing by selecting and connecting pin-pairs that improve the efficiency of length matching. Lee et al [9] studied a mature simultaneous escape routing algorithm [26] and combined it with the length matching of differential pairs based on min-cost median points [27].…”

Section: A Related Workmentioning

confidence: 99%

Obstacle-aware length-matching bus routing

Yan

Chen

2011

Proceedings of the 2011 International Symposium on Physical Design

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As clock frequency increases, signal propagation delay on PCBs is requested to meet the timing specification with very high accuracy. Generally speaking, the net length in a single layer can estimate the routing delay in a single-layer net. In this paper, given a set of r single-layer nets in a bus with their length constraints inside mxn routing grids with s obstacle grids, based on obstacle-aware region partition inside routing grids, obstacle-aware shortest path generation and two detouring operations, R-flip and C-flip, an efficient O(mn+s 3 ) algorithm is proposed to generate the length-matching paths for obstacle-aware bus routing. Compared with the published CAFE router, our proposed routing algorithm can save 80.5% of CPU time to complete obstacle-aware length-matching bus routing with no length error for tested examples on the average.

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Modelling and optimisation algorithm for length‐matching escape routing of differential pairs

Chen

et al. 2019

Electron. lett.

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To improve the performance and signal integrity for printed circuit board designs, considering differential pairs in the escape routing is an important issue. Previous works use two-stage approaches, meeting points determining followed by differential pairs connecting, to generate a routing solution. However, existing approaches may produce either non-length-matching solutions or longer lengthmatching solutions. In this Letter, the authors propose an escape routing model with one-stage optimisation to simultaneously determine median points and route length-matching paths for all differential pairs. Experimental results show that their approach can significantly reduce maximum and average differential-pair skews with 100% length-matching results.

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Escape routing of differential pairs considering length matching

Cited by 9 publications

References 22 publications

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Obstacle-aware length-matching bus routing

Modelling and optimisation algorithm for length‐matching escape routing of differential pairs

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