Error-Correction Coding Using Polynomial Residue Number System

Kalmykov, Igor A.; Pashintsev, V. P.; Tyncherov, K T; Olenev, A. A.; Chistousov, Nikita Konstantinovich

doi:10.3390/app12073365

Cited by 7 publications

(8 citation statements)

References 57 publications

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“…. , p n (x) [77,80]. Since RCs are arithmetic codes, they perform addition, subtraction, and multiplication operations modulo the modules of the code.…”

Section: Implementation Of the Satellite Authentication Methods Using...mentioning

confidence: 99%

Improved Spacecraft Authentication Method for Satellite Internet System Using Residue Codes

et al. 2023

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Low-orbit satellite internet (LOSI) expands the scope of the Industrial Internet of Things (IIoT) in the oil and gas industry (OGI) to include areas of the Far North. However, due to the large length of the communication channel, the number of threats and attacks increases. A special place among them is occupied by relay spoofing interference. In this case, an intruder satellite intercepts the control signal coming from the satellite (SC), delays it, and then imposes it on the receiver located on the unattended OGI object. This can lead to a disruption of the facility and even cause an environmental disaster. To prevent a spoofing attack, a satellite authentication method has been developed that uses a zero-knowledge authentication protocol (ZKAP). These protocols have high cryptographic strength without the use of encryption. However, they have a significant drawback. This is their low authentication speed, which is caused by calculations over a large module Q (128 bits or more). It is possible to reduce the time of determining the status of an SC by switching to parallel computing. To solve this problem, the paper proposes to use residue codes (RC). Addition, subtraction, and multiplication operations are performed in parallel in RC. Thus, a correct choice of a set of modules of RC allows for providing an operating range of calculations not less than the number Q. Therefore, the development of a spacecraft authentication method for the satellite internet system using RC that allows for reducing the authentication time is an urgent task.

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“…. , p n (x) [77,80]. Since RCs are arithmetic codes, they perform addition, subtraction, and multiplication operations modulo the modules of the code.…”

Section: Implementation Of the Satellite Authentication Methods Using...mentioning

confidence: 99%

Improved Spacecraft Authentication Method for Satellite Internet System Using Residue Codes

et al. 2023

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“…Modular codes that are used for computations are of two kinds. These are modular polyalphabetic codes of the reside number system (RNS) [49,50] and modular polyalphabetic polynomial codes [50][51][52]. To organize calculations in the modular polyalphabetic polynomial code, it is necessary to take a set of k irreducible polynomials…”

Section: Development Of An Imitation-resistant Zero-knowledge Authent...mentioning

confidence: 99%

“…Since the irreducible polynomials 1 2 ( ), ( ), ..., ( ) k m x m x m x are defined in GF(2), the modular operations of addition (subtraction) modulo two and multiplication [51,52] are performed in parallel using MPPC. Then, the following equality holds:…”

Section: Development Of An Imitation-resistant Zero-knowledge Authent...mentioning

confidence: 99%

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Improvement of the Cybersecurity of the Satellite Internet of Vehicles through the Application of an Authentication Protocol Based on a Modular Error-Correction Code

Kalmykov,

Olenev,

Kononova

et al. 2024

WEVJ

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The integration of the Internet of Vehicles (IoV) and low-orbit satellite Internet not only increases the efficiency of traffic management but also contributes to the emergence of new cyberattacks. Spoofing interference occupies a special place among them. To prevent a rogue satellite from imposing unauthorized content on vehicle owners, a zero-knowledge authentication protocol (ZKAP) based on a modular polyalphabetic polynomial code (MPPC) was developed. The use of MPPC allowed for increasing the authentication speed of the satellite performing the role of RSU. As a result, a reduction in the time needed to guess the prover’s signal also reduces the probability of granting a rogue satellite the communication session and increases the imitation resistance of the satellite IoV. At the same time, the MPPC allows for improving the noise resistance of the ZKAP. An algorithm for calculating the control residuals for a noise-resistant MPPC was developed for this purpose, as well as an algorithm for correcting errors arising in the communication channel due to interference. Thus, the developed authentication protocol based on a noise-resistant modular code allows for simultaneously reducing the probabilities of the first-order and second-order errors, which leads to the increased cybersecurity of satellite IoV.

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“…In recent decades, the residue number system (RNS) [1][2][3][4][5][6] has been increasingly applied in cryptography [2,7], error correction codes [8], and digital signal processing [3], owing to its carry-free nature and parallel computation. A reduced power consumption, shorter latency, and smaller hardware area can be achieved for applications based on RNS modulation addition [9][10][11][12][13] and multiplication [14][15][16][17][18][19][20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array

Kuo,

2024

Electronics

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A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (2n − 1) multiplier, a modulo (2n) multiplier, and a modulo (2n + 1) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from ⌊n/2⌋ to ⌊n/3⌋ + 1, but it increases the operation complexity for multiplication by three circuits. A hard multiple generator (HMG) is used to address this problem. Two judgment signals in the multi-modulus circuit can be used to perform three operations of the modulo (2n − 1) multiplier, modulo (2n) multiplier, and modulo (2n + 1) multiplier at the same time. The weighted representation is used to reduce the number of partial products. Compared with previously reported methods in the literature, the proposed approach can achieve better performance by being more area-efficient, being faster, consuming low power, and having a lower area-delay product (ADP) and power-delay product (PDP). With the multi-modulus HMG, the proposed modified architecture can save 34.48–55.23% of hardware area. Compared with previous studies on the multi-modulus multiplier, the proposed architecture can save 22.78–35.46%, 4.12–11.15%, 12.59–24.73%, 27.88–38.88%, and 20.49–27.85% of hardware area, delay time, dissipation power, ADP, and PDP, respectively. Xilinx field programmable gate array (FPGA) Vivado 2019.2 tools and the Verilog hardware description language are used for synthesis and implementation. The Xilinx Artix-7 XC7A35T-CSG324-1 chipset is adopted to evaluate the performance.

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Error-Correction Coding Using Polynomial Residue Number System

Cited by 7 publications

References 57 publications

Improved Spacecraft Authentication Method for Satellite Internet System Using Residue Codes

Improved Spacecraft Authentication Method for Satellite Internet System Using Residue Codes

Improvement of the Cybersecurity of the Satellite Internet of Vehicles through the Application of an Authentication Protocol Based on a Modular Error-Correction Code

Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array

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