Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters

Loukrakpam, Merin; Choudhury, Madhuchhanda

doi:10.1007/s00034-019-01062-9

Cited by 3 publications

(12 citation statements)

References 14 publications

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“…For simplified computation, consider the integer part i to be zero and the fraction part f to be between 0 and 1 ( 01 f  ). Taking 2 0.4 as an example, let the input value be 0.4 = 0 + 0.4, where i = 0 and f In recent years, many schemes have been proposed for antilogarithmic conversion systems, such as the straight-line method [3], look-up table method [7,15], shift-and-add method [5,11], bit correction scheme [13], and constant compensation scheme [16]. In 1962, Mitchell [3] first used an approximation method to approximate the antilogarithmic converter, which adopted out = 1 + m to approximate an out = 2 m curve.…”

Section: Antilogarithmic Conversion Methodsmentioning

confidence: 99%

“…In recent years, many schemes have been proposed for antilogarithmic conversion systems, such as the straight-line method [3], look-up table method [7,15], shift-and-add method [5,11], bit correction scheme [13], and constant compensation scheme [16]. In 1962, Mitchell [3] first used an approximation method to approximate the antilogarithmic converter, which adopted out = 1 + m to approximate an out = 2 m curve.…”

Section: Arithmetic Computation Arithmetic Operation Lns-based Operationmentioning

confidence: 99%

“…However, the look-up table scheme demands additional hardware area. Abed and Siferd [5] and Loukrakpam and Choudhury [11] used the shift-and-add scheme to approximate an out = 2 m curve. This method improved the performance in terms of the approximation error, hardware area, and delay, though it had further scope for improvement.…”

Section: Arithmetic Computation Arithmetic Operation Lns-based Operationmentioning

confidence: 99%

“…These require circuits for complex arithmetic computations such as multiplication, division, square root, squaring, and powering, which entail additional hardware costs and longer latency. To reduce the hardware costs and transmission delays, recent studies have developed novel methods to replace the complex arithmetic computations, such as the CORDIC algorithm [1], the table-based algorithm using rectangular multipliers [2], and the logarithmic number system (LNS) [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] to handle arithmetic computations. The CORDIC algorithm [1] uses an iterative method, and is not suitable for three-dimensional real-time DSP because of the limitation of operation speed.…”

Section: Introductionmentioning

confidence: 99%

“…The table-based algorithm using rectangular multipliers [2] requires quite a large hardware memory for storage. The logarithmic number system (LNS) [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] reduces the implementation area and transmission delay for arithmetic computations in DSP. LNS-based arithmetic computation can simplify the complex operations by transforming multiplication to addition, division to subtraction, square root to right shifts, squaring to left shifts, powering to continuous addition, and reciprocals to complementing.…”

Section: Introductionmentioning

confidence: 99%

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Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Kuo

2024

Applied Sciences

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Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

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Section: Antilogarithmic Conversion Methodsmentioning

confidence: 99%

Section: Arithmetic Computation Arithmetic Operation Lns-based Operationmentioning

confidence: 99%

Section: Arithmetic Computation Arithmetic Operation Lns-based Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Kuo

2024

Applied Sciences

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Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability

Loukrakpam

Choudhury

2020

Circuits Syst Signal Process

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Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

Zheng

Zhao²,

Wang³

et al. 2022

Electronics

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In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction evaluation based on an optimized piecewise linear (PWL) method. The proposed segmentor automatically divides nonlinear functions into the fewest segments with a predefined maximum absolute error (MAE) and fractional bit width of the slope. In addition, a multiplier was optimized via Booth encoding to reduce the number of rows in the partial product matrix. Compressors were used to shorten the critical path. The results of application-specific integrated circuit (ASIC) implementation reveal that all metrics of the proposed architecture are improved for single functions, without any compromise. Moreover, reconfigurable technology was introduced for implementing multiple functions while reusing computing resources. Compared to a corresponding architecture without reuse, the area and power of this reconfigurable architecture are reduced by 37.48% and 45.60%, respectively, at the same frequency.

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Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters

Cited by 3 publications

References 14 publications

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability

Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

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