Error analysis of a systolic realization of 2-D filters

Raghuramireddy, D.; Unbehauen, R.

doi:10.1109/78.124967

Cited by 2 publications

(3 citation statements)

References 6 publications

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“…This is due to the fact that the proposed architecture in Fig. 8 has fewer PEs and thus, the lower sum of storage error is obtained in (19) and (21). Consequently, the quantization error is reduced.…”

Section: Error Analysis Of New Digital Filter Architecturesmentioning

confidence: 87%

“…Therefore, the quantized value of is given by (15) where is defined as the storage error caused by storing the output of an adder in a register. In [12], [19], it has been discussed that the rounding operation with a ( )-bit register leads to for fixed-point data arithmetic. Representing the error at the output of PE by and neglecting second-order terms involving and for , 1 and 2, we obtain …”

Section: Error Analysis Of New Digital Filter Architecturesmentioning

confidence: 99%

“…Here, we adopt most notations as defined in [12], [18], [19] to analyze quantization error. For convenience of error analysis, the 2-D local broadcast th order digital filter can be equivalently plotted in Fig.…”

Section: Error Analysis Of New Digital Filter Architecturesmentioning

confidence: 99%

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A new 2-D systolic digital filter architecture without global broadcast

Van

2002

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we propose two-dimensional (2-D) systolic-array infinite-impulse response (IIR) and finite-impulse response (FIR) digital filter architectures without global broadcast, by the hybrid of a modified reordering scheme and a new systolic transformation. This architecture has local broadcast, lower-quantization error, and zero latency without sacrificing the number of multipliers, as well as delay elements under the satisfactory critical period. Furthermore, we extend this new architecture to a useful 2-D systolic cascade-form architecture and provide the comprehensive error analysis for the proposed architectures.Index Terms-Cascade-form architecture, local broadcast, quantization error, systolic architecture, two-dimensional (2-D) digital filter.

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Section: Error Analysis Of New Digital Filter Architecturesmentioning

confidence: 87%

Section: Error Analysis Of New Digital Filter Architecturesmentioning

confidence: 99%

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A new 2-D systolic digital filter architecture without global broadcast

Van

2002

IEEE Trans. VLSI Syst.

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A new 2-D digital filter using a locally broadcast scheme and its cascade form

Van

Tenqchen

Chang

et al.

IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394

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In paperr 'ye propose a new (2-D) systolic-array digital filter using locally broadcast scheme that is the hybrid of a modijied reordering and another systolicThis architecture occlrpies locally broadcusl, lower quantization error and latency IIR digital filter, and N I x N 2 is the order of the IIR digital filter. We deduce the structure under the assumption of N I = N , = N , and then we pay attention to derive 2-D [IR digital filter architecture. For the sake of reducing the critical period, .we apply another systolic transformation as Ivithoi,t .yac,.ificing the of as we[[ as

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Error analysis of a systolic realization of 2-D filters

Cited by 2 publications

References 6 publications

A new 2-D systolic digital filter architecture without global broadcast

A new 2-D systolic digital filter architecture without global broadcast

A new 2-D digital filter using a locally broadcast scheme and its cascade form

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