Erratum: New and unified model for Schottky barrier and III–V insulator interface states formation [J. Vac. Sci. Technol. 16, 1422 (1979)]

Spicer, W. E.; Chye, P.; Skeath, Perry; Su, Cheng‐Kuan; Lindau, I.

doi:10.1116/1.570540

Cited by 109 publications

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“…Most of the previous models for Fermi level pinning assume presence of interface states whose charging screens the metal electronegativity. The origin of the interface states is ascribed to stoichiometry related defect states (Unified Defect model [40]), to metal induced gap states (MIGS model [41,42]) or to disorder induced gap states (DIGS model [43]). …”

Section: Fermi Level Pinning At Metal-semiconductor Interfacesmentioning

confidence: 99%

Electrochemical processes for formation, processing and gate control of III–V semiconductor nanostructures

Hasegawa

Sato

2005

Electrochimica Acta

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This paper reviews recent efforts by authors' group to utilize electrochemical processes for formation, processing and gate control of III-V semiconductor nanostructures. Topics include precise photo anodic and pulsed anodic etching of InP, formation of arrays of <001>-oriented straight nanopores in n-type (001) InP by anodization and their possible applications, and macroscopic and nanometer-scale metal contact formation on GaAs, InP and GaN by a pulsed in-situ electrochemical process, which remarkably reduces Fermi level pinning. All the results indicate that electrochemical processes can achieve unique and important results which the conventional semiconductor technology cannot realize, anticipating their increased importance in future semiconductor nanotechnology and nanoelectronics. Key words:III-V semiconductors, anodic etching, nanopore, electrodeposition, Schottky barrier 1.IntroductionIt is widely recognized that artificial semiconductor nanostructures such as quantum wires (QWRs) and quantum dots(QDs) give rise to new rich functionalities to materials. They produce new quantum state spectra with novel state transitions and linear and non-linear quantum transport phenomena, and open up opportunities for novel quantum devices which control quantum-mechanical behavior of electrons and photons in various sophisticated ways.The standard approach for semiconductor nanostructure formation is to use fine crystal growth techniques such as molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE). To fabricate devices, various standard etching and metal deposition techniques are used together with standard lithography techniques. However, the electrochemical approaches, if it attains sufficiently high controllability at the nanometerscale, seems to be highly useful for nanostructure formation and processing. The expected advantages include: (1) process simplicity and versatility, (2) capability of self-organization, (3) low processing temperature, (4) low process induced damage, (5) precise electrical control and (6) low processing costs.Some well known examples are porous Si formation [1,2] and use of anodized alumina as nanostructure templates for formation of carbon nanotubes [3].The purpose of this paper is to review recent attempts by the authors' group at RCIQE, Hokkaido University, that have been carried out in order to investigate feasibility of utilizing electrochemical processes for nanometer-scale processing and nanostructure formation in III-V semiconductors. Topics discussed in this paper include controlled (1) anodic etching of InP,

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Section: Fermi Level Pinning At Metal-semiconductor Interfacesmentioning

confidence: 99%

Electrochemical processes for formation, processing and gate control of III–V semiconductor nanostructures

Hasegawa

Sato

2005

Electrochimica Acta

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“…The As Ga defects form double donor levels 0.52 eV and 0.75 eV above the valence band. 41 The concentration of these defects can be as high as 10 20 cm Ϫ3 in LT GaAs films grown at 260-270°C. Tunnelling spectroscopy measurements for such samples have shown that these levels broaden to form a midgap deep donor band centered Ӎ0.5 eV above the valence band.…”

Section: A Spectroscopic Signatures Of Compensation In Ga 1àx Mn X Asmentioning

confidence: 99%

Electronic structure and carrier dynamics of the ferromagnetic semiconductorGa1−xMnxAs<

et al. 2003

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Infrared spectroscopy is used to study the doping and temperature dependence of the intragap absorption in the ferromagnetic semiconductor Ga 1Ϫx Mn x As, from a paramagnetic, xϭ0.017 sample to a heavily doped, xϭ0.079 sample. Transmission and reflectance measurements coupled with a Kramers-Kronig analysis allow us to determine the optical constants of the thin films. All ferromagnetic samples show a broad absorption resonance near 200 meV, within the GaAs band gap. We present a critical analysis of possible origins of this feature, including a Mn-induced impurity band and intervalence band transitions. The overall magnitude of the real part of the frequency dependent conductivity grows with increasing Mn doping, and reaches a maximum in the xϭ0.052 sample where T C saturates at the highest value (ϳ70 K) for the series. We observe spectroscopic signatures of compensation and track its impact on the electronic and magnetic state across the Mn phase diagram. The temperature dependence of the far infrared spectrum reveals a significant decrease in the effective mass of itinerant carriers in the ferromagnetic state. A simple scaling relation between changes in the mass and the sample magnetization suggest that the itinerant carriers play a key role in producing the ferromagnetism in this system.

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“…As a possible origin of the FLP at the metal=semiconductor interface, metal-induced gap states (MIGS), 24) bond polarization, 25) disorder-induced gap states (DIGS) 26) or defects 27) have been long discussed. In this work, we reexamine the FLP on n-Ge on the basis of the MIGS model, that is, the tail of the electron wave function in a metal is intrinsically penetrated into the semiconductor.…”

mentioning

confidence: 99%

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

Nishimura

Yajima

Toriumi

2016

Appl. Phys. Express

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The element metal/germanium (Ge) interface exhibits a strong Fermi level pinning (FLP), which is usually characterized on the basis of Ge side semiconductor properties. In this work, we demonstrate that metal properties significantly affect the Schottky barrier height (SBH) on Ge. Metallic germanides show both FLP alleviation and a clear substrate orientation dependence of SBH on Ge, despite the nearly perfect FLP and very slight orientation dependence in the element metal case. As a result, ohmic characteristics are observed at germanide/n-Ge (111) junctions. The metal properties required to alleviate the FLP on Ge are also discussed. © 2016 The Japan Society of Applied Physics G ermanium (Ge) is one of the promising semiconductor materials for high-performance complementary metal-oxide-semiconductors (CMOSs) in the next generation owing to its high electron and hole mobilities. Recently, high electron mobility in Ge n-channel metal-insulation-semiconductor field-effect transistors (n-MISFETs) with a sub-nm equivalent oxide thickness gate stack has been demonstrated, owing to appropriate gate stack designing, [1][2][3][4] in addition to the high hole mobility in Ge p-MISFET, which has already been reported. 5,6) Therefore, the most serious challenges for realizing practical scaled Ge CMOS are currently the reduction in parasitic resistance and the suppression of off-state leakage at the source=drain of MISFETs. In particular, to reduce the contact resistance at the metal=Ge interface, a reduction in Schottky barrier height (SBH) at the interface is definitely required. However, the Fermi level is almost perfectly pinned to the valence band edge of Ge at the metal=Ge interface for various element metals. 7,8) This fact suggests that the Fermi level pinning (FLP) on Ge may be limited by an intrinsic mechanism. Therefore, understanding the FLP mechanism and controlling the SBH on n-Ge are strongly required.Recently, FLP alleviation has been demonstrated in ultrathin-film [GeO 2 , 9) Al 2 O 3 , 9) GeN, 10) SiN,11) MgO,12) Si,13) ZnO, 14) TiO 2 , 15) W-encapsulating Si, 16) indium tin oxide (ITO) 17) ] insertion at the element metal=Ge interface. When the direct metal=Ge interface is replaced by the metal= ultrathin film and ultrathin film=Ge interfaces, the strong FLP at the direct metal=Ge interface becomes less significant. Nevertheless, since the interface layer resistance is added, the direct metal=Ge interface with a low SBH is more preferable from the viewpoint of contact resistance reduction. With respect to the direct metal=Ge interface, it has recently been reported that the SBHs at epitaxial Fe 3 Si, 18) α-TiGeN, 19) epitaxial Mn 5 Ge 3 , 20) epitaxial NiGe 2 , 21) graphene, 22) and Sn 23) =n-Ge interfaces are relatively low, which deviates from the trend of strong FLP. 7,8) Some of them 18,20,21,23) considered that the FLP on Ge might not be determined by an intrinsic but extrinsic origin. It is inferred that those two kinds of experimental results may include a key aspect to understand the FLP mechani...

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Erratum: New and unified model for Schottky barrier and III–V insulator interface states formation [J. Vac. Sci. Technol. 16, 1422 (1979)]

Abstract: Articles you may be interested inErratum: Use of Raman spectroscopy to characterize strain III-V epilayers: Application to InAs on GaAs(001) grown by molecularbeam epitaxy [J.Addendum: Cryopump measurements relating to safety, pumping speed, and radiation outgassing [J.

Cited by 109 publications

References 0 publications

Electrochemical processes for formation, processing and gate control of III–V semiconductor nanostructures

Electrochemical processes for formation, processing and gate control of III–V semiconductor nanostructures

Electronic structure and carrier dynamics of the ferromagnetic semiconductorGa1−xMnxAs<

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

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