Equivalent Sheet Resistance of Intrinsic Noise in Sub-100-nm MOSFETs

Chen, Chih‐Hung; Lee, R.; Tan, Ge; Chen, D. C.; Lei, Peiming; Yeh, Chih‐Jung

doi:10.1109/ted.2012.2198651

Cited by 9 publications

(4 citation statements)

References 21 publications

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“…For this purpose, we first studied the impact of JleJJon Rnsh using (9) in [4] to calculate the channel thermal noise Sid and (2) in [4] to calculate the gm numerically (i.e., gm = aJ D / aV G s)'…”

Section: Reason Behind the Themementioning

confidence: 99%

“…Here we used UMC's 65 nm [4] and 28 nm CMOS technology nodes as benchmarks. Since these papers only reported their on-resistances Ron obtained at VDS = 50 mV and the extracted external resistance Rex" we evaluate their channel resistance at VDS = 50 mV as Rch = Ron -Rex!…”

Section: Recent Device Performancementioning

confidence: 99%

“…[18] • MIT 20 run [19] • SEMATECH 50 11m [20] to, UMC 65 run [4] * UMC28run Channel Length L (nm) Figure 5: Rnsh for the p-type FETs as afunction of channel length L using the measured Ron, Rex" and the peak gmfrom TSMC's 40 nm Ge FinFET (e) [2i], and UMC 65 nm CMOS (I:::. ) [4] technology node.…”

Section: Recent Device Performancementioning

confidence: 99%

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Future CMOS technology for low noise integrated circuit designs

Chen

Cheng

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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This paper utilizes the recently defined equivalent noise sheet resistance to study the noise perfonnance of fu ture sub-lOOnm MOSFETs using strain engineering, channel engineering with III -V materials, and quantum well structures for low-noise applications. Experimental results for devices fabricated in UMC's five different CMOS technology nodes and other published data down to 20 nm technology node are demonstrated. Strategies for the future low-noise technologies are also discussed.

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Section: Reason Behind the Themementioning

confidence: 99%

Section: Recent Device Performancementioning

confidence: 99%

See 1 more Smart Citation

Future CMOS technology for low noise integrated circuit designs

Chen

Cheng

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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“…Chen technologies using the equivalent noise sheet resistance [4], the investigation of device reliability [5]- [7], and the thermal noise modeling of devices [8]- [10]. Due to the gate-to-source and the gate-to-drain capacitances, the gate resistance cannot be directly characterized from the I -V measurements.…”

Section: Introductionmentioning

confidence: 99%

Extraction of Gate Resistance in Sub-100-nm MOSFETs With Statistical Verification

Chen

Tsai

Chen

et al. 2014

IEEE Trans. Electron Devices

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This paper presents an improved z-parameter based approach to extract the gate resistance at low frequencies. The effectiveness of this approach, compared with other y-parameter based approaches, is verified using 430 samples fabricated in 40-, 55-, 90-, and 110-nm CMOS technology nodes. The influence of the nonquasi-static (NQS) effect, resulting from the distributed channel resistance, on the gate resistance extraction is studied, and the optimum processes are suggested to reduce the NQS effect. Finally, the extraction of the channel resistance in the lightly doped drain region is also presented.

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