Equivalence Checking

Kuehlmann, Andreas; Somenzi, Fabio; Hsu, Chih-Jen; Bustan, Doron

doi:10.1201/b19714-6

Cited by 2 publications

(5 citation statements)

References 56 publications

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“…In the BLOCKCUBE(q, Q, F k ) procedure, described in Algorithm 7, the queue of proof obligations is initialized with (q, k), encoding the fact that q must be blocked in F k (line 2). Then, proof obligations are iteratively extracted from the queue and discharged (lines [3][4][5][6][7][8][9][10][11][12][13][14].…”

Section: Ic3mentioning

confidence: 99%

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Hardware Model Checking Algorithms and Techniques

Cabodi,

Camurati,

Palena

et al. 2024

Algorithms

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Digital systems are nowadays ubiquitous and often comprise an extremely high level of complexity. Guaranteeing the correct behavior of such systems has become an ever more pressing need for manufacturers. The correctness of digital systems can be addressed resorting to formal verification techniques, such as model checking. Currently, it is usually impossible to determine a priori the best algorithm to use given a verification task and, thus, portfolio approaches have become the de facto standard in model checking verification suites. This paper describes the most relevant algorithms and techniques, at the foundations of bit-level SAT-based model checking itself.

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Section: Ic3mentioning

confidence: 99%

“…During the last two decades, research in the field of formal verification has led to the development of many techniques. Such techniques can be subdivided into three main approaches to formal verification: theorem proving [4,5], equivalence checking [6] and model checking [7,8].…”

Section: Introductionmentioning

confidence: 99%

Hardware Model Checking Algorithms and Techniques

Cabodi,

Camurati,

Palena

et al. 2024

Algorithms

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“…Practical EC approaches typically assume a known or guessed correspondence between the storage elements of the circuit, so that the checking can be reduced to a Combinational Equivalence Checking (CEC) problem. CEC is a mature technology, with known limitations but also with tools and solutions for practical industrial cases [1].…”

Section: Formal Verification Background and Related Workmentioning

confidence: 99%

“…This approach is used by many academic and commercial tools, as it avoids state explosion. The mapping of storage elements can be derived from naming conventions or it can be automated [1].…”

Section: Formal Verification Background and Related Workmentioning

confidence: 99%

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Formal Verification of Fault-Tolerant Hardware Designs

Entrena,

Sánchez-Clemente,

García-Astudillo

et al. 2023

IEEE Access

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Digital circuits for space applications can suffer from operation failures due to radiation effects. Error detection and mitigation techniques are widely accepted solutions to improve dependability of digital circuits under Single Event Upsets (SEUs) and Single Event Transients (SETs). These solutions imply design modifications that must be validated. This paper presents a formal verification method to prove that the applied fault tolerance techniques do actually prevent fault propagation as well as that the fault-tolerant circuit is functionally equivalent to the original version. The method has been implemented in an in-house software tool, VeriHard. It has been successfully applied to verify a wide variety of fault tolerance techniques, such as Triple Modular Redundancy (TMR), Duplication with Comparison (DwC), Safe Finite State Machines and Hamming encoding. Experimental results with benchmarks and industrial cases illustrates the capabilities of the method and its high performance.

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Equivalence Checking

Cited by 2 publications

References 56 publications

Hardware Model Checking Algorithms and Techniques

Hardware Model Checking Algorithms and Techniques

Formal Verification of Fault-Tolerant Hardware Designs

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