Epitaxial Realignment of In-Situ Doped Polycrystalline Silicon for Advanced BiCMOS Technologies

Abstract

Industrial feasibility of an in-situ-doped (ISD) polycrystalline Si process using chemical vapor deposition for advanced BiCMOS technologies is presented. ISD As-doped amorphous and polycrystalline Si layers have been deposited on Si substrates at 610°C and 660°C, respectively, with the deposition rate varying from 120 to 128Å /minute. Samples are compared on the basis of having been subjected to a substrate preclean prior to deposition using an HF solution and an in-situ H2 bake. TEM micrographs reveal the presence of a thin (10-15 Å) native oxide at the deposited layer/substrate interface for samples not precleaned. This is confirmed for both the amorphous and polycrystalline Si depositions. However, for the 610°C-deposited samples given the substrate preclean, a polycrystalline structure with partial epitaxial layer growth is observed. Twins and stacking faults are found at the poly Si/single crystal Si interface, causing interfacial roughness. Post-deposition annealing of the Si films typically generates grain growth, but RBS-channeling characterization of the annealed Si provides evidence of some recrystallization, the extent of which is affected by the original growth condition. Analysis shows that the amorphous deposition at 610°C results in a mixture of epitaxial and polycrystalline Si. Epitaxial realignment of the polycrystalline Si film by post deposition annealing can result in significantly improved device performance.