Epitaxial III−V Nanowires on Silicon

Abstract

We present results of ideal epitaxial nucleation and growth of III−V semiconductor nanowires on silicon substrates. This addresses the long-time challenge of integrating high performance III−V semiconductors with mainstream Si technology. Efficient room-temperature generation of light on silicon is demonstrated by the incorporation of double heterostructure segments in such nanowires. We expect that advanced heterostructure devices, such as resonant tunneling diodes, superlattice device structures, and heterostructure photonic devices for on-chip communication, could now become available as complementary device technologies for integration with silicon.

Surface-Guided Core–Shell ZnSe@ZnTe Nanowires as Radial p–n Heterojunctions with Photovoltaic Behavior

“…13 Moreover, their ability to relieve strain radially 13 while maintaining high crystallinity and the flexibility of their growth process enables the creation of unconventional material interfaces with high lattice mismatch. 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 3 Nanowire heterostructures, both axial and radial, are being investigated extensively for optoelectronic applications, 15 partly because they enable various degrees of freedom for band engineering. When considering radial heterostructures in particular, different configurations were tailored to fit specific requirements: For a high electron mobility system, a type I core-shell was designed to confine charge carriers in the core region while potentially reducing scattering from the nanowire surface.…”

Electrical contacts to single nanowires: a scalable method allowing multiple devices on a chip. Application to a single nanowire radial p-i-n junction

“…In the last few years, part of the scientific and technological interest in nanowires has been moved to energy harvesting such as photovoltaic [4][5][6][7][8][9][10][11][12][13], thermoelectric devices [14][15][16][17] and batteries [18][19][20][21][22]. Most of these devices are linked to the external world via electrical contacts.…”

Influence of growth temperature on growth of InGaAs nanowires in selective-area metal–organic vapor-phase epitaxy

“…Because lattice strain allows elastic deformation without introducing misfit dislocations due to ultra-small growth regions [6], it is possible to achieve integration of III-V compound NWs on silicon platform [7]. One of the major approaches for growing NWs is a catalyst-assisted vapor-liquid-solid (VLS) method, which includes however the possibility of catalyst incorporation, leading to lower quality NWs.…”