Envelope tracking power amplifier with static predistortion linearization

Rautio, Timo; Harju, Henri; Hietakangas, Simo; Rahkonen, Timo

doi:10.1002/cta.549

Cited by 16 publications

(20 citation statements)

References 9 publications

(5 reference statements)

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“…This is further emphasized for increased signal bandwidth [4]. As mentioned, the signal bandwidth is increased from 1MHz [3] to 4MHz.…”

Section: Timing Errormentioning

confidence: 93%

“…V DD -drives) [3] In [3], ET transmitter with linear 0.5W 1GHz LDMOS power amplifier with constant compression envelope yielded drain efficiency of 41% and power added efficiency of ca. 39%.…”

Section: Introductionmentioning

confidence: 99%

“…This work expands [3] by increasing the input bandwidth up to 4MHz and finding the simplest possible means to Section II describes our measurement setup and signal specifications. In Sect.…”

Section: Introductionmentioning

confidence: 99%

“…This paper is a further study of a well-documented (ET) and (EER) transmitter environment [1]- [3]. The environment is built around data sequencer implemented on a Xilinx Virtex-II FPGA and the following test setups has been published:…”

Section: Introductionmentioning

confidence: 99%

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Comparison of static and memory predistortion in envelope tracking system

Neitola

Rahkonen

2013

2013 Norchip

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This paper concentrates on finding optimal yet simple predistorter for an amplifier in envelope tracking (ET) system. The scope is to linearize AM-AM error statically by maintaining constant compression by polynomial fit to the envelope path. For static AM-PM predistortion, the path delay between RF and envelope paths is fixed. A set complex memory predistorters were also tested and compared to the static prediction. It was found that the ET transmitter linearity can be further improved by a simple memory predistorter by taking the path timing into account.

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“…This is further emphasized for increased signal bandwidth [4]. As mentioned, the signal bandwidth is increased from 1MHz [3] to 4MHz.…”

Section: Timing Errormentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Comparison of static and memory predistortion in envelope tracking system

Neitola

Rahkonen

2013

2013 Norchip

Self Cite

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“…However, in the case of ignoring the output power level, the EER system has very low gain in lowpower regions due to the influence of the saturated operation of switching PA and the constant-envelope phase-modulated RF input signal [8]. Meanwhile, the envelope tracking (ET) PA, another popular efficiency enhancement technique, has been proposed in [8][9][10][11][12][13][14][15]. The technique modulates the supply voltage of the PA according to the input power level to reduce the dc power consumption at low power, but typically suffers from a complex system and a sophisticated supply modulator [10].…”

Section: Introductionmentioning

confidence: 98%

A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

Zhu

2016

Wireless Pers Commun

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This paper describes the design and implementation of a low-power CMOS class-E Chireix RF outphasing power amplifier (PA) for WLAN applications. The proposed circuit is based on cascode class-E topology with two-stage structure and Chireix power combiner with a floating load. This class-E topology adopts self-biased technique and current-reused technique that avoids using thick-oxide transistors and can enhance the driving ability and power gain. Additionally, the Chireix combiner can reduce the loss of power and improve the efficiency by avoiding the use of isolation resistance. With a 2.5 V power supply, the realized prototype achieved 21.4 dBm of maximum output power and 29.9 % of average power-added efficiency (PAE) at 2.4 GHz. When operated for minimum input levels at 2.5 V, it reached 38.8 dB power gain. For a WLAN OFDM signal with 20 MHz, the error vector magnitude of 3 % is achieved with peak drain efficiency of 62 %. Moreover, the outphasing power amplifier is fully integrated with TSMC 0.18-lm CMOS technology and the chip area including testing pads is 1.07 9 1.17 mm 2 .

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Reducing the power envelope fluctuation of OFDM systems using side information supported amplitude clipping approach

Taher

Mandeep

Ismail

et al. 2013

Circuit Theory & Apps

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OFDM is an important modulation technique currently in development in the field of communications systems. OFDM signals can combat multipath propagation and fading channels and can support large data rates. However, OFDM systems are multicarrier systems and experience problems due to the required summation of sinusoids when the in‐phase subcarriers are combined, which produces high power peaks. The large power envelope fluctuations that occur at the output cause in‐band and out‐of‐band distortions that result in degraded BER performance. The literature contains many qualified approaches to resolving the peak‐to‐average power ratio problem, including selected mapping, partial transmit sequence, and amplitude clipping techniques. The simplest technique is the amplitude clipping technique, and the selected mapping and partial transmit sequence techniques are excessively complicated for real‐time implementation. In this paper, we suggest a modification to the amplitude clipping method to produce a novel clipping technique called the side information supported amplitude clipping (SI‐SAC) method. The SI‐SAC technique involves sending certain bits of extra information so that the receiver can recover all of the clipped data. The SI‐SAC technique does not add computational complexity to the system, and simulation results show that the proposed method is superior to the conventional method. The peak‐to‐average power ratio was reduced by ≈2.5 dB, and the magnitude of the mean squared error vector is the same as that of the original signal that is not clipped. In contrast, the conventional amplitude clipping method produces a mean squared error vector with a large magnitude. Copyright © 2012 John Wiley & Sons, Ltd.

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Envelope tracking power amplifier with static predistortion linearization

Cited by 16 publications

References 9 publications

Comparison of static and memory predistortion in envelope tracking system

Comparison of static and memory predistortion in envelope tracking system

A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

Reducing the power envelope fluctuation of OFDM systems using side information supported amplitude clipping approach

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