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Cited by 2 publications
(2 citation statements)
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“…[1,4,10,11,17,22,44,54,58,63,92,93,97,103,112,120,126,130,137,138,143,144] Für die Taktverteilung sind 4 primäre und 4 sekundäre Global-LLs vorgesehen.…”
Section: Programmable Logic Device Pldunclassified
“…[1,4,10,11,17,22,44,54,58,63,92,93,97,103,112,120,126,130,137,138,143,144] Für die Taktverteilung sind 4 primäre und 4 sekundäre Global-LLs vorgesehen.…”
Section: Programmable Logic Device Pldunclassified
“…• SD asynchroner Setzeingang (Set) und RD 1,3,9,10,18,24,44,53,56,60,86,87,89,97,105,111,118,123,129,130,134,135] …”
Section: Fpga Mit Antifuse-linkmentioning
confidence: 99%
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