Ensemble Monte Carlo study of interface-state generation in low-voltage scaled silicon MOS devices

Ellis-Monaghan, John; Hulfachor, R.B.; Littlejohn, M. A.

doi:10.1109/16.502424

Cited by 21 publications

(4 citation statements)

References 30 publications

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“…However, all of these investigators used a single per condition. Several authors [5]- [8], applying Monte Carlo or other simulation techniques to NMOSFET's, have predicted that at drain voltages below about 3 V, electrons heated by e-e scattering (EES) should dominate the high energy tail of the electron energy distribution function (EEDF) above . Thus, EES events should play an increasingly important role in the HC degradation of NMOSFET's as the supply voltage is scaled down.…”

Section: Introductionmentioning

confidence: 99%

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Rauch

Guarin

LaRosa

1998

IEEE Electron Device Lett.

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The hot carrier degradation of short channel NMOS-FET's (L L L EFF = = = 0.07-0.10 m) stressed at 2.0 V V DS V DS V DS 2.9 V and a wide V GS V GS V GS range is shown NOT to obey the classic hot carrier "lucky electron model." In the low and mid V GS V GS V GS range, the degradation behavior is better described by an effective electron temperatures model proposed here, which takes e-e scattering effects into account. In the high V GS V GS V GS regime, a further lifetime reduction can be qualitatively explained within this model by the increase in electron concentration at the Si-SiO 2 interface near the drain region.Index Terms-Accelerated stress, e-e scattering, effective electron temperatures, hot carrier degradation, interface state generation, lifetime projection, lucky electron model, reliability.

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Section: Introductionmentioning

confidence: 99%

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Rauch

Guarin

LaRosa

1998

IEEE Electron Device Lett.

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“…low Schottky-barrier MOSFETs [19]) are receiving special attention. Other groups have studied also the dynamic behaviour of MOSFET devices based on transient EMC simulations [20] and the constant field scaling was analysed for gate lengths down to 120 nm by Ellis-Monaghan et al [21] by means of a particle-based simulator in order to describe the influence of hot-carrier injection in the oxide. However, to the author's knowledge, a detailed EMC study of the consequences of constant field scaling on the highfrequency dynamic behaviour (with small-signal equivalent circuit parameters evaluated directly from transient EMC simulation) of sub-100 µm has not been performed up to date.…”

Section: Introductionmentioning

confidence: 99%

Towards the nanoscale: influence of scaling on the electronic transport and small-signal behaviour of MOSFETs

Rengel¹,

Pardo²,

Martín³

2004

Nanotechnology

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In this work, the influence of downscaling bulk MOSFETs below the 100 nm range on their static and dynamic behaviour is analysed by means of a particle-based Monte Carlo simulator. Internal transport conditions are investigated throughout the extensive information provided by numerical simulations (electric fields, concentration, velocity and energy of carriers, energy bands, etc), and a physical interpretation is given to the dynamic behaviour observed. Results show that even when the most favourable downscaling conditions are considered (that is, following the constant field scaling rules), significant two-dimensional electrostatic effects, together with reduced gate control, lead to the degradation of important figures of merit such as gate-to-source capacitance, transconductance or maximum oscillation frequency. Conventional MOSFET geometries are therefore near to a limit when reaching gate lengths of 50 nm, and the use of alternative solutions is necessary in order to maintain the proper electrostatic behaviour of a ‘well-tempered’ transistor.

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“…Electron-electron scattering (EES) has been proposed to be another possible energy-gain mechanism which provides additional energy to the channel electrons for sub-3V electron injection [67,68,69,70,71,72]. The role of EES in heating the electrons above energy qV ds was mainly studied by means of simulation in the literature.…”

Section: Electron-electron Scattering (Ees) Model and The Refined Effmentioning

confidence: 99%

Impact of channel engineering on hot-electron injection in the deep-submicrometer flash memory cell

Zhang¹

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First and foremost, I would like to express my deepest gratitude to my project supervisor, Dr. Ang Diing Shenp, for his patient guidance, invaluable advice, persistent support and encouragement throughout the entire course of the project, without which the completion of the project would not have been possible. His devotion and determination towards scientific research have greatly inspired me to strive not only for the research project but also for my professional career in future. I also wish to offer my sincere thanks to Mr. Tan Kok Tong, the project co-supervisor in Systems on Silicon Manufacturing Company (SSMC) Pte. Ltd, for giving me this great opportunity to pursue a higher degree in the field of advanced semiconductor technology. Special appreciation goes to my SSMC mentor, Mr. Kuan Hing Poh, who had given me very helpful suggestions and willingly shared his knowledge on Flash memory technology. I am also grateful to Mr. Glen Foo and Mr. Derek Sim, for the enlightening discussion we had as well as their kindness in sharing the testing machine with me. In addition, I am indebted to my family members, especially my parents and grandparents, for their continuous love and moral support all along. I also want to take this opportunity to thank my dearest Tony for his great understanding as well as encouragement during the course of the project. Last but not least, I would like to extent my sincere thanks to all my colleagues in the Sensors & Actuators Lab II (NTU), as well as the engineers in the Section of Failure Analysis and Reliability (SSMC), for their help in making this project successful. Finally, I am grateful to SSMC for providing the research scholarship and the test devices used in this research project.

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Ensemble Monte Carlo study of interface-state generation in low-voltage scaled silicon MOS devices

Cited by 21 publications

References 30 publications

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Towards the nanoscale: influence of scaling on the electronic transport and small-signal behaviour of MOSFETs

Impact of channel engineering on hot-electron injection in the deep-submicrometer flash memory cell

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