Enhancing Transition Fault Model for Delay Defect Diagnosis

Cheng, Wu-Tung; Benware, B.; Guo, Ruifeng; Tsai, Kun-Han; Kobayashi, Takeo; Maruo, K.; Nakao, Minoru; Fukui, Yoshiaki; Okada, H.

doi:10.1109/ats.2008.44

Cited by 37 publications

(19 citation statements)

References 11 publications

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“…For illustration we consider ISCAS-89 benchmark circuit s 27 under the test shown in Figure 1 More sophisticated definitions [12]- [17] can be used instead of the basic ones to deal with differences between the observed response of a faulty circuit and the responses of modeled faults.…”

Section: Responses Of X-faultsmentioning

confidence: 99%

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

Pomeranz

2011

2011 Sixteenth IEEE European Test Symposium

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This paper studies issues related to transition fault diagnosis using multicycle broadside tests that are applied at-speed. Two transition fault models were proposed earlier for at-speed simulation, referred to as d -faults and x -faults. Both fault models account for the extra delay of a transition fault in order to allow at-speed simulation. However, they differ in the following ways. (1) The number of x -faults is equal to the number of conventional transition faults, while the number of d -faults grows with the number of cycles in a test. (2) Output responses of x -faults contain unspecified values that result in lower diagnostic resolution. The paper describes a fault diagnosis procedure that combines the use of x -faults for efficiency with the use of d -faults for diagnostic resolution.

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Section: Responses Of X-faultsmentioning

confidence: 99%

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

Pomeranz

2011

2011 Sixteenth IEEE European Test Symposium

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“…it assumes a single defect for each failing pattern. Similar concept has been applied to diagnose at-speed defect using path delay fault models [6] [7] or gate transition delay fault models [8] [9] [10]. While SLAT concept has been shown to be effective for diagnosing manufacturing defect, it may not be sufficient for speed path debug where multiple paths are exercised in a single test pattern.…”

Section: Introductionmentioning

confidence: 98%

Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using atspeed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

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“…Another scenario where fault effects of a transition fault propagate to an observed output through pulses is the following [10]. Suppose that a fault effect propagates to multiple inputs of a gate G. Using the D notation to indicate lines carrying fault effects, suppose that one input of G has the value D, and another input has the value D during the second pattern of a test.…”

Section: Introductionmentioning

confidence: 99%

“…Fault diagnosis procedures [1]- [10] determine the locations of defects in a circuit that failed during the application of a test set. Based on the observed output response of the circuit, a fault diagnosis procedure finds candidate faults whose presence in the circuit is the most likely explanation to the observed response.…”

Section: Introductionmentioning

confidence: 99%

“…In [10], hazards are used in a postprocessing step to augment the set of candidate faults found by a fault diagnosis process that ignores hazards. In this paper we consider the use of the hazard-based detection conditions instead of the conventional detection conditions during fault diagnosis in order to capture some of the additional fault effects and obtain more accurate diagnosis results based on transition faults.…”

Section: Introductionmentioning

confidence: 99%

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Resolution of Diagnosis Based on Transition Faults

Pomeranz

Reddy

2012

IEEE Trans. VLSI Syst.

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The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gatelevel circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

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Enhancing Transition Fault Model for Delay Defect Diagnosis

Cited by 37 publications

References 11 publications

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

Speed-Path Debug Using At-Speed Scan Test Patterns

Resolution of Diagnosis Based on Transition Faults

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