Enhancing random-pattern coverage of programmable logic arrays via masking technique

Fujiwara, Hideo; Fujisawa, O.; Hikone, Kazunori

doi:10.1109/test.1988.207847

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…It was suggested in [21] that a small number, one or two, of mask lines be used for F-PLAs to keep the area overhead at a moderate level. The Fujiwara's RPT PLAs are called F-PLAs in this paper.…”

Section: Previous Workmentioning

confidence: 99%

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On the design of random pattern testable PLA based on weighted random pattern testing

Reddy

1992

J Electron Test

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Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fan-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random pattems to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.

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Section: Previous Workmentioning

confidence: 99%

“…The number of mask lines for F-PLAs affects fault coverage and area overhead [20]- [21]. According to the experimental results of [21], F-PLAs with two bit mask lines and two product mask lines achieve the highest fault coverage with moderate area overhead.…”

Section: Number Of Test Patterns and Fault Coveragementioning

confidence: 99%

On the design of random pattern testable PLA based on weighted random pattern testing

Reddy

1992

J Electron Test

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A new 18nm FinFET-based Programmable Logic Array type Multiplexer for High-speed and Low-Power applications

Jeevan,

Sivani

2023

2023 IEEE 20th India Council International Conference (INDICON)

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Enhancing random-pattern coverage of programmable logic arrays via masking technique

Cited by 2 publications

References 8 publications

On the design of random pattern testable PLA based on weighted random pattern testing

On the design of random pattern testable PLA based on weighted random pattern testing

A new 18nm FinFET-based Programmable Logic Array type Multiplexer for High-speed and Low-Power applications

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