Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Abstract

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by glueing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called Pcircuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%.

A Novel Logic Detection Algorithm for Logic Circuits

“…A n-variables Boolean function may be represented canonically in a sum-of-products form as [10], [11] f…”

Testability of Switching Lattices in the Cellular Fault Model

“…The first description of lattices for implementing Boolean functions is due to a seminal paper by Akers in 1972 [1]. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest [2], [3], [4], [5], [7], [8], [10], [11], [12].…”

Testability of Switching Lattices in the Stuck at Fault Model

“…The idea of using regular two-dimensional arrays of switches to implement Boolean functions dates back to a seminal paper by Akers in 1972 [2], but has found a renewed interest recently, thanks to the development of a variety of nanoscale technologies. Synthesis algorithms targeting lattices of multi-terminal switches have been designed [3], [5], [13], [14], and methods based on function decomposition techniques have been exploited to mitigate the cost of implementing switching lattices [8], [9], [10]. Moreover, several studies on fault tolerance for nano-crossbar arrays have been published recently [4], [15], [16], [17].…”