Enhancing DRAM printing process window by using inverse lithography technology (ILT)

Chu, Chia‐Chi; Tsao, Becky; Chiou, Karl; Lee, Snow; Huang, Jerry; Liu, Yong; Lin, Tim; Moore, Andrew W.; Pang, Liang

doi:10.1117/12.657015

Cited by 6 publications

(4 citation statements)

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“…The same analysis was then applied to the SEM images from the left (Figs. [16][17][18], corner (Figs. [19][20][21], and bottom of the array (Figs.…”

Section: Real Mask Shows Curvilinear Mask Patterns Have Smaller Varia...mentioning

confidence: 99%

“…[1][2][3][4][5][6][7][8] Then in 2005 and 2006, Luminescent Technologies (later acquired by Synopsys and KLA) introduced the industry's first commercial product and the author coined the name of this technology: inverse lithography technology (ILT). [9][10][11][12][13][14][15][16][17] ILT is a rigorous computational approach that determines the mask shapes that will produce the desired on-wafer results. Given a target wafer shape and models of the lithographic optics, an inverse calculation is made to arrive at the mask pattern that will supply the desired wafer result and the best process window.…”

Section: Introduction 1curvilinear Masks Started From Curvilinear Inv...mentioning

confidence: 99%

See 1 more Smart Citation

Curvilinear mask metrology: what is the equivalent critical dimension?

Pang,

Seal,

Boettiger

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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“…The same analysis was then applied to the SEM images from the left (Figs. [16][17][18], corner (Figs. [19][20][21], and bottom of the array (Figs.…”

Section: Real Mask Shows Curvilinear Mask Patterns Have Smaller Varia...mentioning

confidence: 99%

Section: Introduction 1curvilinear Masks Started From Curvilinear Inv...mentioning

confidence: 99%

Curvilinear mask metrology: what is the equivalent critical dimension?

Pang,

Seal,

Boettiger

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

View full text Add to dashboard Cite

“…[1][2][3][4][5][6][7][8] Then in 2005 and 2006, Luminescent Technologies (later acquired by Synopsys and KLA) introduced the industry's first commercial product and the author coined the term inverse lithography technology (ILT) for this approach. [9][10][11][12][13][14][15][16][17] ILT is a rigorous computational approach to determine the mask shapes that will produce the desired on-wafer results. Given a target wafer shape and models of the lithographic optics, an inverse calculation is made to arrive at the mask pattern that will supply the desired wafer result and the best process window.…”

Section: Curvilinear Ilt Started Over a Decade Agomentioning

confidence: 99%

Breakthrough curvilinear ILT enabled by multi-beam mask writing

Pang

Russell

Baggenstoss

et al. 2021

J. Micro/Nanopattern. Mats. Metro.

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Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today's advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical "hotspots" on chips, but had not been used for entire chips.Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops. Approach:The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement-partitioning and stitching-has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time.Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies-a doubling in the wafer process windowfor semiconductor manufacturing.

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“…1.1 Full-Chip, Curvilinear ILT is Now a Practical Reality Inverse lithography technology (ILT)-a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results-has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Since its introduction more than a decade ago, [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] there have been numerous studies that demonstrate that curvilinear ILT mask shapes, in particular, produce the best process windows. 18 However, until recently, the runtimes associated with this computational technique have limited its practical application to critical "hotspots" on chips.…”

Section: Introductionmentioning

confidence: 99%

Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization

Pang,

Lu,

Russell

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer cooptimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Technology. The full-chip ILT technology employed, first demonstrated in a paper presented at the 2019 SPIE Photomask Technology Conference, produces curvilinear ILT mask patterns without stitching errors, and with process windows enlarged by over 100% compared to the OPC process of record, while the mask was written by multibeam mask writer. At the 2020 SPIE Advanced Lithography Conference, a method was introduced in which MWCO is performed during ILT optimization. This approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within a practical, 12-h time frame, while also producing the largest process windows. We first review MWCO technology, then curvilinear ILT mask patterns written by VSB mask writer, and then show the corresponding 193i process wafer prints. Evaluations of mask write times and mask quality in terms of critical dimension uniformity and process windows are also presented.

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Enhancing DRAM printing process window by using inverse lithography technology (ILT)

Cited by 6 publications

References 0 publications

Curvilinear mask metrology: what is the equivalent critical dimension?

Curvilinear mask metrology: what is the equivalent critical dimension?

Breakthrough curvilinear ILT enabled by multi-beam mask writing

Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization

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