Enhancing and Exploiting Contiguity for Fast Memory Virtualization

Alverti, Chloe; Psomadakis, Stratos; Karakostas, Vasileios; Gandhi, Jayneel; Nikas, Konstantinos; Goumas, Georgios; Koziris, Nectarios

doi:10.1109/isca45697.2020.00050

Cited by 26 publications

(16 citation statements)

References 57 publications

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“…Speculation. In speculation-based approaches [19], [21], [52], [53], a missing translation is predicted, the processor continues executing instructions speculatively, and a validation page walk is performed in the background. Those approaches are affected by the system state (OS, fragmentation) as they depend on allocating contiguous virtual pages to contiguous physical pages to the missing address translations.…”

Section: E Interaction With Os Page Replacement Policymentioning

confidence: 99%

“…Prior work has quantified the cost of TLB performance [6]- [9] and has proposed approaches to mitigate the overheads of address translation. These approaches mainly fall into three categories: (i) increasing TLB reach by introducing hardware and OS support [6], [10]- [15], (ii) reducing the latency of TLB misses [7], [16]- [21], and (iii) reducing TLB misses by prefetching Page Table Entries (PTEs) [22]- [25]. In this paper we focus on the last category, TLB prefetching, that operates at the microarchitecture level, is independent of the system state, relies only on the memory access pattern of the application, and does not disrupt the existing virtual memory subsystem.…”

Section: Introductionmentioning

confidence: 99%

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Exploiting Page Table Locality for Agile TLB Prefetching

Vavouliotis

Alvarez

Karakostas

et al. 2021

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

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Frequent Translation Lookaside Buffer (TLB) misses incur high performance and energy costs due to page walks required for fetching the corresponding address translations. Prefetching page table entries (PTEs) ahead of demand TLB accesses can mitigate the address translation performance bottleneck, but each prefetch requires traversing the page table, triggering additional accesses to the memory hierarchy. Therefore, TLB prefetching is a costly technique that may undermine performance when the prefetches are not accurate.In this paper we exploit the locality in the last level of the page table to reduce the cost and enhance the effectiveness of TLB prefetching by fetching cache-line adjacent PTEs "for free". We propose Sampling-Based Free TLB Prefetching (SBFP), a dynamic scheme that predicts the usefulness of these "free" PTEs and prefetches only the ones most likely to prevent TLB misses. We demonstrate that combining SBFP with novel and state-of-theart TLB prefetchers significantly improves miss coverage and reduces most memory accesses due to page walks.Moreover, we propose Agile TLB Prefetcher (ATP), a novel composite TLB prefetcher particularly designed to maximize the benefits of SBFP. ATP efficiently combines three low-cost TLB prefetchers and disables TLB prefetching for those execution phases that do not benefit from it. Unlike state-of-the-art TLB prefetchers that correlate patterns with only one feature (e.g., strides, PC, distances), ATP correlates patterns with multiple features and dynamically enables the most appropriate TLB prefetcher per TLB miss.To alleviate the address translation performance bottleneck, we propose a unified solution that combines ATP and SBFP. Across an extensive set of industrial workloads provided by Qualcomm, ATP coupled with SBFP improves geometric speedup by 16.2%, and eliminates on average 37% of the memory references due to page walks. Considering the SPEC CPU 2006 and SPEC CPU 2017 benchmark suites, ATP with SBFP increases geometric speedup by 11.1%, and eliminates page walk memory references by 26%. Applied to big data workloads (GAP suite, XSBench), ATP with SBFP yields a geometric speedup of 11.8% while reducing page walk memory references by 5%. Over the best state-of-the-art TLB prefetcher for each benchmark suite, ATP with SBFP achieves speedups of 8.7%, 3.4%, and 4.2% for the Qualcomm, SPEC, and GAP+XSBench workloads, respectively.

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Section: E Interaction With Os Page Replacement Policymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting Page Table Locality for Agile TLB Prefetching

Vavouliotis

Alvarez

Karakostas

et al. 2021

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Prefetched Address Translation [29] (ASAP) utilises layout configurations in the operating system to approximate direct translation, and thus speculatively break linked-list chains in two-dimensional radix tables. Alverti et al [6] rearrange virtual mappings to better provide locality, for prediction.…”

Section: Virtualisation and Translationmentioning

confidence: 99%

Compendia: reducing virtual-memory costs via selective densification

Ainsworth

Jones

2021

Proceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management

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Virtual-to-physical memory translation is becoming an increasingly dominant cost in workload execution; as data sizes scale, up to four memory accesses are required per translation, and 24 in virtualised systems. However, the radix trees in use today to hold these translations have many favourable properties, including cacheability, ability to fit in conventional 4 KiB page frames, and a sparse representation. They are therefore unlikely to be replaced in the near future.In this paper we argue that these structures are actually too sparse for modern workloads, so many of the overheads are unnecessary. Instead, where appropriate, we expand groups of 4 KiB layers, each able to translate 9 bits of address space, into a single 2 MiB layer, able to translate 18 bits in a single memory access. These fit in the standard huge-page allocations used by most conventional operating systems and architectures. With minor extensions to the page-table-walker structures to support these, and aid in their cacheability, we can reduce memory accesses per walk by 27%, or 56% for virtualised systems, without significant memory overhead.CCS Concepts: • Software and its engineering → Virtual memory; • Computer systems organization → Architectures.

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“…Pham et al applied speculation to glue together regions of large pages that have been splintered by the hypervisor [38]. Alverti et al used contiguous allocations and a page table walk predicting mechanism along with speculation to minimize page walk latencies [11]. The above methods could be applied to our approach to reduce latencies as well.…”

Section: B Related Workmentioning

confidence: 99%

Perforated Page: Supporting Fragmented Memory Allocation for Large Pages

Park

Cha

Kim

et al. 2020

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

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The availability of large pages has dramatically improved the efficiency of address translation for applications that use large contiguous regions of memory. However, large pages can be difficult to allocate due to fragmented memory, non-movable pages, or the need to split a large page into regular pages when part of the large page is forced to have a different permission status from the rest of the page. Furthermore, they can also be expensive due to memory bloating caused by sparse accesses to application data. In this work, we enable the allocation of large 2MB pages even in the presence of fragmented physical memory via perforated pages. Perforated pages permit the OS to punch 4KB page-sized holes in the physical address range allocated to a large page and re-map them to other addresses as needed. This not only enables the system to benefit from large pages in the presence of fragmentation, but also allows for different permissions to exist within a large page, enhancing sharing flexibility. In addition, it allows unused parts of a large page to be used elsewhere, mitigating memory bloating. To minimize changes to the system, perforated pages reuse the 4KBlevel page table entries to store the hole locations and translates holes into regular 4KB pages. For performance, the proposed technique caches the translations for hole pages in the TLBs and track holes via cached bitmaps in the L2 TLB. By enabling large pages in the presence of physical memory fragmentation, perforated pages increase the applicability and resulting benefits of large pages with only minor changes to the hardware and OS. In this work, we evaluate the effectiveness of perforated pages with timing simulations under diverse and realistic fragmentation scenarios. Our results show that even with fragmented memory, perforated pages accomplish 93.2% to 99.9% of the performance achievable by ideal memory allocation, and 2.0% to 11.5% better performance over the conventional system running with fragmented memory.

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Enhancing and Exploiting Contiguity for Fast Memory Virtualization

Cited by 26 publications

References 57 publications

Exploiting Page Table Locality for Agile TLB Prefetching

Exploiting Page Table Locality for Agile TLB Prefetching

Compendia: reducing virtual-memory costs via selective densification

Perforated Page: Supporting Fragmented Memory Allocation for Large Pages

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