Enhancing an x86_64 multi-core architecture with data-flow execution support

Abstract-The path towards future high performance computers requires architectures able to efficiently run multi-threaded applications. In this context, dataflow-based execution models can improve the performance by limiting the synchronization overhead, thanks to a simple producer-consumer approach. This paper advocates the ISE of standard cores with a small hardware extension for efficiently scheduling the execution of threads on the basis of dataflow principles. A set of dedicated instructions allow the code to interact with the scheduler. Experimental results demonstrate that, the combination of dedicated scheduling units and a dataflow execution model improve the performance when compared with other techniques for code parallelization (e.g., OpenMP, Cilk).

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“…We enhanced computing clusters with a variant of the micro-architecture proposed in [21], [29] (see figure 2).…”

Section: Distributed Scheduler -Dsmentioning

confidence: 99%

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions

Mondelli

Scionti³

et al. 2015

2015 Euromicro Conference on Digital System Design

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“…Its challenging goal was to develop a dataflow based execution model on standard off-the-shelf cores [10] [11]. Additional analysis lead to exploration of execution over faulty components [25] and applicability to the Haskell and Transactional Memory [7].…”

Section: Related Workmentioning

confidence: 99%

A matrix multiplier case study for an evaluation of a configurable dataflow-machine

Verdoscia

Vaccaro

Giorgi

2015

Proceedings of the 12th ACM International Conference on Computing Frontiers

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Configurable computing has become a subject of a great deal of research given its potential to greatly accelerate a wide variety of applications that require high throughput. In this context, the dataflow approach is still promising to accelerate the kernel of applications in the field of HPC. That tanks to a computational dataflow engine able to execute dataflow program graphs directly in a custom hardware. On the other hand, evaluating radically different models of computation remains yet an open issue. In this paper we present as case study the matrix multiplication that constitutes the fundamental kernel of the linear algebra. The evaluation takes into account the execution of the matrix product both in non-pipelined and pipelined modes. Results obtained running the execution of the two modes on an FPGA-based demonstrator show the validity of the configurable Dataflow-Machine. Moreover, at the same throughput, the power consumption is expected to be lower than in clock-based systems.

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“…In such memory model a combination of consumer-producer patterns [23], [24] and transactional memory [25], [26] permits a novel combination of data-flow concepts and transactions in order to address the consistency across nodes, where each node is assumed to be cachecoherent, i.e., like in a classical multi-core. Data-flow models also allows the system to take care in a distributed way of faults that may affect a node [27], [28]: in essence a data-flow thread may be re-executed without side effects since we retain its input before scheduling anything else on the same core.…”

Section: Related Workmentioning

confidence: 99%

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Giorgi

2015

2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing

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Embedded System toolchains are highly customized for a specific System-on-Chip (SoC).\ud When the application needs more performance, the designer is typically forced\ud to adopt a new SoC and possibly another toolchain.\ud The rationale for not scaling performance by using, e.g., two SoCs, is\ud that maintining most of the operations on-chip may allow for higher energy efficiency.\ud We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC.\ud This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards.\ud A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer.\ud In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach

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Enhancing an x86_64 multi-core architecture with data-flow execution support

Cited by 12 publications

References 9 publications

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions

A matrix multiplier case study for an evaluation of a configurable dataflow-machine

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

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