Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security

Kocabaş, Övünç; Savaş, Erkay; Großschädl, Johann

doi:10.1109/reconfig.2008.59

Cited by 11 publications

(17 citation statements)

References 5 publications

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“…RSA with 2048 bits has been confirm to consume higher energy and therefore unsuitable for WSN applications and embedded system (Amin et al, 2008a). Moreover, RSA when implemented in hardware demand large silicon area and therefore increase the size of the chip (Kocabas et al, 2008b). An alternative to RSA is Elliptic Curve Cryptography (ECC) and Advance Encryption System (AES).…”

Section: Fig 2 Standard Tpm Componentsmentioning

confidence: 99%

“…1, are achievable through PKC implementation supporting asymmetric key management as well as authenticity and integrity. Although the use of PKC in WSN is previously denied due to its high resourced (energy, memory and computational) (Yong et al, 2006), many recent works have proved its feasibility in the WSN area (Kocabas et al, 2008b). Latest, Wen Hu (Hu et al, 2009) used Trusted Platform Module hardware which is based on Public Key (PK) platform to augment the security of the sensor node.…”

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confidence: 99%

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Integrity Enhancement in Wireless Sensor Networks

Yussoff¹,

Hashim²,

Abidin³

2010

Smart Wireless Sensor Networks

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Section: Fig 2 Standard Tpm Componentsmentioning

confidence: 99%

mentioning

confidence: 99%

Integrity Enhancement in Wireless Sensor Networks

Yussoff¹,

Hashim²,

Abidin³

2010

Smart Wireless Sensor Networks

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“…The implementation of instructions for efficient integer and logic operations have been explained earlier in our earlier work [13]. Therefore, we focus only on explaining new instructions that allow secure execution of cryptographic operations; but only a couple of instructions, which we think are the most representative of the adopted methodology, are explained for space considerations.…”

Section: The New Instruction Set Architecturementioning

confidence: 99%

Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms

Durahim

Savaş

Yumbul

2009

2009 International Conference on Reconfigurable Computing and FPGAs

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Abstract-We design and realize a protected zone inside a reconfigurable and extensible embedded RISC processor for isolated execution of cryptographic algorithms. The protected zone is a collection of processor subsystems such as functional units optimized for high-speed execution of integer operations, a small amount of local memory, and generaland special-purpose registers. We outline the principles for secure software implementation of cryptographic algorithms in a processor equipped with the protected zone. We also demonstrate the efficiency and effectiveness of the protected zone by implementing major cryptographic algorithms, namely RSA, elliptic curve cryptography, and AES in the protected zone. In terms of time efficiency, software implementations of these three cryptographic algorithms outperform equivalent software implementations on similar processors reported in the literature. The protected zone is designed in such a modular fashion that it can easily be integrated into any RISC processor; its area overhead is considerably moderate in the sense that it can be used in vast majority of embedded processors. The protected zone can also provide the necessary support to implement TPM functionality within the boundary of a processor.

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“…In our earlier work appeared in the poster session of Reconfig'08 [22], we proposed a cryptographic unit (CU) that accelerates cryptographic algorithms such as RSA, elliptic curve cryptography (ECC) and AES. It has been shown that the proposed CU can easily be integrated to any RISC processor including the embedded end of the processor spectrum.…”

Section: Related Work and Our Contributionmentioning

confidence: 99%

“…In this paper, we explore the benefits of a cryptographic unit (CU) in the context of isolated execution of cryptographic algorithms, a preliminary prototype of which has originally been proposed for secure and efficient implementation of cryptographic algorithms [22]. The cryptographic unit (CU) is relatively low cost executional unit that can be integrated to many RISC-style processors.…”

Section: Introductionmentioning

confidence: 99%

Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit

Yumbul

Savaş

2009

Proceedings of the 2nd International Conference on Security of Information and Networks - SIN '09

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Cryptographic algorithms handle sensitive information and their safe execution plays an essential role in many security applications. When implemented in software on generalpurpose computers, cryptographic algorithms are vulnerable to a variety of attacks such as side-channel and cold-boot attacks since they either share hardware resources with other simultaneously executing processes or store sensitive information in easily accessible places (e.g. main memory). In this paper, we demonstrate that secure and isolated execution of cryptographic algorithms is possible on a cryptographic unit that can easily be integrated to all RISC processors. The cryptographic unit is capable of physically isolating the execution of cryptographic algorithms from all other simultaneously executing processes. By specifically providing an AES implementation running in this isolated execution environment we demonstrate that it is possible to provide physical process isolation for cryptographic algorithms without any significant overhead in execution time. Furthermore, the proposed technique protects the cryptographic applications against cold-boot and cache attacks as well as any other threats originated from other processes since the sensitive material never leave the cryptographic unit. We realized a RISC-based embedded processor with five-stage pipeline featuring the cryptographic unit on an FPGA device. We included the implementation results both for FPGA and ASIC realizations.

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Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security

Cited by 11 publications

References 5 publications

Integrity Enhancement in Wireless Sensor Networks

Integrity Enhancement in Wireless Sensor Networks

Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms

Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit

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