Enhancement of test data compression with multistage encoding

Sivanantham, S.; Padmavathy, M; Gopakumar, G.; Mallick, P. S.; Perinbam, J. Raja Paul

doi:10.1016/j.vlsi.2013.12.001

Cited by 16 publications

(7 citation statements)

References 48 publications

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“…At the same time, our scheme meets safe threshold of capture power. Table 8 shows the storage, compression ratio and the average power of the proposed scheme against Dual MP-LFSR reseeding [34], 9C-RLHC code [32] and low-power LFSR reseeding [35]. Experimental results show the proposed scheme precedes other scheme, except for the storage volume of s38417.…”

Section: Resultsmentioning

confidence: 99%

“…As shown in Table 6, to demonstrate the effectiveness of the proposed scheme in achieving high test data compression, we compare the compression ratio of the proposed scheme with that of 9C-RLHC [32], hybrid coding [31] and reseeding of dividing [33] (The follow-up experimental results are attained under the threshold of 15%). Hybrid coding and reseeding of dividing use the same test set with our scheme.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYLinear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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“…There are several multi-stage compression are available to improve the compression ratio [7]. The runlength encoding and Huffman encoding are mixed in order to reduce the test volume, test power, test application time.…”

Section: Related Workmentioning

confidence: 99%

Improvement of test data compression using combined encoding

Mirthulla

Arulmurugan

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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Developments in process technology have led to the design of systems with millions of transistors on a single chip and it has resulted in an increase of test data required to test the circuits.Conventional external testing processes involve storing all test vectors and test responses on the automatic test equipment (ATE) memory. The test data volume for the scan-based test is normally very large due to its single pattern length generated using a combinational automatic test pattern generation (ATPG) tool. The test application time depends on the amount of test data stored on ATE, the time required to transfer the test data from ATE to the core and length of the scan chain. But these testers have limited memory, speed and I/O channels. Efficient test data reduction techniques can reduce the testing time, test power and ATE memory requirements. Three multistage compression techniques are introduced to reduce the test data volume in scan-test applications. The three encoding schemes namely equal run-length coding (ERLC), extended frequency directed runlength (EFDR) coding, alternating variable runlength (AVR) is used for computing the data. These encoding scheme together with nine coded (9C) technique enhance the test compression ratio. In the first stage, pre-generated test cubes with unspecified bits are encoded using nine-coded (9C) scheme. Later the three encoding schemes utilize the properties of compressed data to enhance the test compression. This multistage compression is effective especially when the percentage of don't care in a test set is very high. The experimental result obtained from ISCAS'89 benchmark circuit confirms the average compression ratio of 46%, 52%, 57% with the proposed 9C-ERLC, 9C-EFDR, 9C-AVR codes respectively.

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“…The compression methods such as alternating FDR (ARL) coding [22], extended FDR (EFDR) coding [21,32], alternating variablelength (AVR) coding [24], equal-run-length coding (ERLC) [22], alternating frequency-directed equal-run-length coding (AFDER) [33], low-power selective pattern compression (LP-SPC), [34] and Shifted Alternating FDR coding [35] consider both runs of 0s as well as 1s to form the codewords. The ARL code [22] is also a variable-to-variable length code.…”

Section: Introductionmentioning

confidence: 99%

“…Several Huffman based compression techniques such as variable-input Huffman coding, variable-to-variable Huffman coding, optimal selective Huffman coding, complementary Huffman coding and run-length based Huffman coding (RLHC) available to improve the compression efficiency, area overhead and the test application time [37]. Many low-power compression techniques are available in the literature for the minimization of test power, test data volume and test time [8,[33][34][35]. In observation-oriented test pattern generation with the scan-chain disabling technique, the test pattern generation process is assisted by testability analysis to generate the observation-oriented test patterns.…”

Section: Introductionmentioning

confidence: 99%

Test Data Compression with Alternating Equal-Run-Length Coding

Sivanantham¹,

S²,

Ramki³

et al. 2018

IJET

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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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Enhancement of test data compression with multistage encoding

Cited by 16 publications

References 48 publications

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Improvement of test data compression using combined encoding

Test Data Compression with Alternating Equal-Run-Length Coding

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