Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy

Abstract

We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (') varies as a function of MTJ dimension, MTJs with dual interfaces show ' over 60 at 20nm node, while MTJs of single interface show ' around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/'), ~1/2 level of single interface MTJs.

Nano-engineered architectures for ultra-low power wireless body sensor nodes

“…This tradeoff is used in our circuit-level characterization (Section 4.1.2). For example, for a ∆ of 27, a threshold write current I co of 170 , and a nominal switching time of 1ns [Park12], we can relax the write current to 150 if we have a pulsewidth of 25ns.…”

Magnetic tunnel junctions for magnetic field sensor by using CoFeB sensing layer capped with MgO film

“…Recently, MTJs with MgO capping layers for memory cells have been suggested for making PMA enlarge both the top and bottom interfaces with MgO films in CoFeB free layers. [5][6][7][8][9] In the current study, we evaluate the MTJ structure of a CoFeB sensing layer capped with an MgO film to obtain two interfaces of MgO/CoFeB exhibiting interfacial PMA in order to improve the controllability of the characteristics in MTJs for magnetic field sensors. EXPERIMENT We used MTJs with Ta/Ru (1 nm)/PtMn (15 nm)/CoFe (2 nm)/Ru (0.9 nm)/CoFeB (2.3 nm)/MgO (t barrier nm)/CoFeB (t CoFeB )/MgO (t cap nm)/Ta structures in the experiment.…”

0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

“…All the simulations examined here were performed using the HSPICE program with a predictive technology model for a 20nm FinFET [16] and our developed STT-MTJ macromodel [10]. The STT-MTJ parameters were determined by reference to recently reported STT-MTJs [17][18][19], as shown in Table I. Assuming the usage of a device process for the full-swing operation, the threshold voltages V th of the FinFETs for the low-voltage operation were set to the same as those for the fullswing (0.9V) operation.…”