Enhancement-Mode Gate-Recess-Free GaN-Based p-Channel Heterojunction Field-Effect Transistor With Ultra-Low Subthreshold Swing

Tungsten-Gated GaN/AlGaN p-FET With Imax > 120 mA/mm on GaN-on-Si

“…2(h), The maximum drain currents of p-FETs in this study are found to roughly follow the classic 1 L G scaling law. E-mode operation could be obtained through a deeper gate recess etch, or the introduction of hydrogen or oxygen plasma treatment in the gate region [11], [27], [15].…”

Depletion- and Enhancement-Mode p-Channel MISHFET Based on GaN/AlGaN Single Heterostructures on Sapphire Substrates

“…We have employed the given material parameters, and only modified the valence band offset according to [21] by adjusting the electron affinity of AlGaN. The surface potential was set to 𝜑𝜑 s = 1.6 eV [17], and the relaxation of the GaN channel was also taken into account. The measured carrier concentration values are quite close to the theoretical prediction.…”

“…Reported p-channel transistors realized by metalorganic vapor phase epitaxy (MOVPE) are typically based on an Al(In)GaN barrier with an unintentionally doped (uid) GaN channel layer on top, both grown This work was supported in part by the Deutsche Forschungsgemeinschaft under Grant VE 597/3-1 "C-GaN" pseudomorphically on a relaxed GaN buffer [3][4][5][6][7][8][9][10][11][12][13][14]. Furthermore, p-GaN-gated HEMT structures, originally developed for high-power switches, have been most recently utilized to investigate p-channel devices [15][16][17][18][19][20]. The doubleheterostructure design typically results in the formation of a 2DEG below and a 2DHG above the Al(In)GaN barrier [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]40].…”

“…Furthermore, p-GaN-gated HEMT structures, originally developed for high-power switches, have been most recently utilized to investigate p-channel devices [15][16][17][18][19][20]. The doubleheterostructure design typically results in the formation of a 2DEG below and a 2DHG above the Al(In)GaN barrier [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]40]. This can be advantageous for monolithic integration of n-and p-channel devices [6][7][8]20] on the same wafer, but it could also be an issue due to parasitic coupling of n-and pchannels, leakage at elevated temperature etc.…”

Gate Leakage and Reliability of GaN -Channel FET With SiNₓ/GaON Staggered Gate Stack

“…Meanwhile, the commercial GaN-on-Si p-GaN gate highelectron-mobility-transistor (HEMT) platform (based on the p-GaN/AlGaN/GaN epi-structure) for power applications is also compelling and progressively exploited for constructing p-FETs and CL circuits [7], [13], [14], [15], [16], [17], [18]. Although not intentionally designed for p-FETs, this platform boasts several advantages compared to purely 2DHG-based structures, including the readily available p-GaN layer, the inherent decoupling of n-/ p-channels, and a good integration capability with key devices to be served, e.g., p-GaN gate power HEMTs [7], [16].…”