Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers

Zurla, Riccardo; Cabrini, A.; Pasotti, M.; Torelli, G.

doi:10.1109/icecs.2016.7841147

Cited by 5 publications

(2 citation statements)

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“…For example, the method which uses flipped voltage follower (FVF) as a voltage buffer not only achieves the same compensation effect but also improves GBW compared with conventional voltage buffer compensation [31]. What's more, in [32], the proposed method achieves a high GBW by adding a gain stage in series with the voltage buffer. However, these improved methods cannot get rid of the limitation of output swing.…”

Section: Introductionmentioning

confidence: 99%

“…Note that neither of the above technologies can enhance GBW since the frequency of the non-dominant pole is not improved compared with that of the two-stage SMC amplifier. Some modified techniques based on voltage buffer compensation can enhance GBW were proposed in previous works [31], [32]. For example, the method which uses flipped voltage follower (FVF) as a voltage buffer not only achieves the same compensation effect but also improves GBW compared with conventional voltage buffer compensation [31].…”

Section: Introductionmentioning

confidence: 99%

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A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique

et al. 2020

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A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a 0.18 µm CMOS technology and the chip area of it is about 0.076mm 2. The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3 • , respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/µs average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only 108µW , proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability. INDEX TERMS Two-stage amplifier, current efficiency, frequency compensation, inner feedforward path.

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Section: Introductionmentioning

confidence: 99%