Enhanced Trench Shielded Power UMOSFET for Single Event Burnout Hardening

Krishnamurthy, Saranya; Kannan, Ramani; Hussin, Fawnizu Azmadi; Yahya, Erman Azwan

doi:10.1109/rsm46715.2019.8943495

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…Existing research has shown that before the occurrence of SEB or SEGR in SiC MOSFETs, phenomena such as gate leakage current I G and drain leakage current I D increases occur [15,17,18]. Among them, the mechanism of an SEB effect is the occurrence of an abnormal bulk current, which leads to a sharp increase in the lattice temperature of the device, resulting in a local thermal burnout of the device [19][20][21][22][23]; the mechanism of the SEGR effect is that a transient additional electric field is generated in the gate dielectric layer that exceeds the critical electric field, causing the gate oxide layer to be broken down [14,[24][25][26][27]. But, the specific occurrence of SEB or SEGR is closely related to the location of the formation of an internal leakage current in the device.…”

Section: Introductionmentioning

confidence: 99%

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

Xiang,

Liang,

Feng

et al. 2023

Electronics

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A leakage current is the most critical parameter to characterize heavy ion radiation damage in SiC MOSFETs. An accurate and refined analysis of the source and generation process of a leakage current is the key to revealing the failure mechanism. Therefore, this article finely tests the online and post-irradiation leakage changes and leakage pathways of SiC MOSFETs caused by heavy ion irradiation, analyzes the damaged location of the device in reverse, and discusses the mechanism of leakage generation. The experimental results further confirm that an increase in the leakage current of a device during heavy ion irradiation is positively correlated with the applied voltage of the drain, but the leakage path is not direct from the drain to the source. The experimental analysis of the source of the leakage current of the device after irradiation indicates that there is also a leakage current path between the device gate and source. The research results suggest that the experimental sample is more prone to a single-event gate rupture effect under this heavy ion radiation condition. The gate breakdown mainly occurs in the gate oxide layer at the neck region. This research can provide a theoretical basis for the radiation resistance reinforcement of SiC power devices.

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Section: Introductionmentioning

confidence: 99%

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

Xiang,

Liang,

Feng

et al. 2023

Electronics

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show abstract

“…With the continuous development of the aerospace technology, especially for the deep space probe and other extreme conditions, the SiC MOSFETs are significantly suitable. However, many researchers have found that SiC power MOSFETs are susceptible to heavy-ion radiation in the space environment [4][5][6]. The high-energy heavy-ion can cause serious radiation damage in the SiC MOSFET even at the drain voltages below the breakdown voltage (BV).…”

Section: Introductionmentioning

confidence: 99%

“…Catastrophic failure has been found to occur at about half the rated BV for the commercial VDMOSFET devices by the heavy-ion irradiation experiments [7][8][9]. So far, many researches have been carried out for the SiC VDMOSFET to investigate the mechanism of SEB event [5][6][7][8][9]. The most effective and common way to improve the anti-irradiation ability of the SiC MOSFET is adding a buffer layer between the epilayer and substrate to decrease the strong electric field and high impact ionization rate after an ion's strike.…”

Section: Introductionmentioning

confidence: 99%

Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Zhou

Wang

2022

J. Phys.: Conf. Ser.

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Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.

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High Single-Event Burnout Resistance 4H-SiC Junction Barrier Schottky Diode

Cao

et al. 2021

IEEE J. Electron Devices Soc.

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This paper presents a single-event burnout (SEB) resistance method for 4H-SiC Junction Barrier Schottky Diode (JBS) under high bias voltage and linear energy transfer (LET) conditions. The method is validated via two-dimensional numerical simulations. The analysis and comparison of conventional 4H-SiC JBS and 4H-SiC Multi-Buffer Layer JBS (MBL-JBS) diodes verify the resistance tolerance of the latter device to SEB. Silvaco TCAD simulation results prove that the 4H-SiC MBL-JBS modulates the drift region's electric field distribution and disperses the high-peak electric field at the N-/N+ junction. Moreover, it reduces the impact generation rate at the Schottky, PN and N-/N+ junctions to achieve SEB tolerance. The device's SEB performance is optimized by adjusting the 4H-SiC MBL-JBS structure parameters, and the SEB threshold voltage is significantly improved compared with the traditional structure.

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Enhanced Trench Shielded Power UMOSFET for Single Event Burnout Hardening

Cited by 8 publications

References 6 publications

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

High Single-Event Burnout Resistance 4H-SiC Junction Barrier Schottky Diode

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