Enhanced thermally induced stress effect on an ultrathin gate oxide

Abstract

The effects of thermal stress on the electrical characteristics of metal-oxide-semiconductor diodes with oxides in an ultrathin regime were studied. By centering a quartz ring as a heat sink beneath the silicon wafer, the introduced temperature gradient results in a corresponding hat-like shape thickness distribution for an oxide grown on the wafer with a rapid thermal processing system. The enhanced exterior tensile and compressive thermal stresses due to introduced temperature gradient make the oxides exhibit less and more substrate injection saturation current J sat , respectively, in comparison to control oxides. Their flatband voltage V FB data also clearly show the dependency of effective charge number density N eff on exterior thermal stress. A stress distribution model is proposed to explain the observation. Co-60 irradiation was also performed on the stressed samples to observe this stress extent by examining the variation of electrical characteristics. It was found that an oxide grown on a wafer in exterior compression exhibited better radiation hardness than one in tension.

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

“…In fact, the interface states and the bulk traps determine the level and slope of J-V curve in the inversion region, respectively. For the current saturation mechanism of thermal SiO , Si atom on the surface of the wafer was consumed to grow SiO while the saturation current level increases with oxide thickness under 30 regime [27]. But for the Al O gate dielectrics, the oxidation of the "as-deposited" Al film consumes sparse Si atoms and therefore produces thinner SiO and fewer bulk traps.…”

“…For an anodization time longer than 5.0 minutes, excessive anodization may consume more Si atoms to grow thicker SiO . Consequently, more traps at the SiO Si-substrate interface will be created [27] and the C is therefore increased with the anodization time. The turn around points with the lowest EOT, , and C in Fig.…”

Microwave irradiation impact on Ta2O5stack capacitors with different gates

“…The same is observed for W-gated capacitors, but only for the thinnest layers (figure 5(c)). This phenomenon may be associated with film/substrate stress [29]. If there is external tensile stress on the Si substrate, then the Si band gap is enlarged which reduces the intrinsic carrier concentration and leads to lower leakage current.…”

Thickness-dependent stress effect in p-type metal–oxide–semiconductor structure investigated by substrate injection current

“…However, a thicker oxide consumes a larger volume of Si, which may contribute to higher interface and bulk trap densities, increasing J sub . 18 So the trap-related effect dominates the J sub behavior of devices for different oxide thicknesses. Figure 2 shows the dependencies of J sub and the extracted gate capacitance (C ext ) of the devices on the thick and thin wafers.…”