Enhanced Hardware Implementation of Hybrid Stochastic Neural Network using FPGA

Abstract

Most of the traditional digital implemented systems uses fixed point or floating point for representing and processing data. An alternative approach is to represent data as random bits that are distributed along the sequence. To be precise, stochastic logic can be considered as a solution for hardware size for application that consume physical area like neural networks as it uses logic gates to implement complex operations and its inherits resistance to bit flips noise. To avoid some of the problems that this type of processing suffers from, a combination of stochastic logic and classical logic (fixed point) is used to implement a neural networks (Fully connected feed-forwards) that is characterized by FPGA large size consuming. The stochastic logic is utilized have to implement part of the multiplication operations in the hidden layers of network and LFSR is used as a random generator for conversion of weights and activation functions outputs. The hardware utilization of Spartan 3E-500K FPGA results are compared with another network of the same size. A discussion of some of the issues that related to this methodology faces is also presented.