Enhanced Device Stability of Ionic Gating Molybdenum Disulfide Transistors

Abstract

The application of ion gels as gate dielectrics having an excellent mechanical flexibility and high capacitance to molybdenum disulfide (MoS2) devices has been extensively studied; however, some issues remain unaddressed with regard to device stability such as gate leakage current, hysteresis, and bias stress instability. This study suggests a fabrication process for the ionic gating of the MoS2 device to enhance the device stability by laminating the ion gel film onto the MoS2 transistor using a cut‐and‐stick method and adding a passivation layer to remove unintentional parasitic capacitances generated by the capacitive coupling effect. The ionic gating MoS2 transistor fabricated via this process operates at a low voltage (<1 V) and exhibits superior electrical characteristics such as low gate leakage currents (≈10−11 A), high on–off ratio (>106), and low hysteresis (<0.05 V). To further investigate the device stability, bias stress instability of the ionic gating MoS2 transistor is examined. The charge‐trapping mechanism is the main cause of threshold voltage shifts under gate bias stress.

Synthesis of two‐dimensional transition metal dichalcogenides for electronics and optoelectronics

“…Otherwise, quenching of the phonon mode in the proton‐conductor‐gated MoS 2 channel also contributes to the high mobility. Yang et al 163 introduced an ionic‐gated dielectric transistor. Figure 11D shows schematic of the process for fabricating the ionic gating MoS 2 transistor with lateral gate using the cut‐and‐stick method.…”

“…D, Schematic of the process for fabricating the ionic gating MoS 2 transistor with lateral gate using the cut‐and‐stick method. Reproduced with permission from Reference 163. E, Structural diagram of the CaF 2 gate FET.…”