Industrial WLAN devices suffer from interface delay and poor CPU performance, which would incur an inevitable cost of throughput for aggregation schemes. An enhanced aggregation scheduler is proposed. In this proposed method, the originator's behaviour in both the upper media access control (MAC) and the lower MAC layer is modified. The originator pre-stores subframes of the next aggregated data units despite that the block Ack is not received. Through utilising the modified method, the hardware delay overhead was minimised. Implementation on own chipset indicates that with this aggregation scheduler, higher throughput can be achieved than conventional scheduler, especially when using high rates. Introduction: Frame aggregation schemes are proposed in 802.11 n/ac/ ad to boost the performance of high-throughput WLANs [1]. It was originally known in 802.11n as one of the significant improvement, where two types of frame aggregation schemes were introduced, the aggregate media access control (MAC) service data unit (A-MSDU) and the aggregate MAC protocol data unit (A-MPDU). Block Ack frame is used to acknowledge the aggregated data units using a block Ack information field and a bitmap field. The bitmap subfield is 128 octets in length and is used to indicate the received status of up to 64 data units. Bit position n of the block Ack bitmap, if set to 1, acknowledges receipt of a subframe with the sequence control value equal to (block Ack starting sequence (SS) control + n). Bit position n of the block Ack bitmap, if set to 0, indicates that a subframe with sequence control value equal to (block Ack SS control + n) has not been received [2, 3]. However, there is currently no aggregation scheduler designed specifically for industrial WLAN devices. In non-aggregation transmissions, lost data units are retransmitted by the hardware. Nevertheless, the aggregated subframes can only be retransmitted by the upper layer due to limited RAM resources in industrial implementations. Currently, most portable wireless devices use interfaces such as secure digital input and output (SDIO), universal serial bus (USB) and serial peripheral interface (SPI). However, those interfaces suffer from huge command overhead and small clock frequency. Poor CPU performance would also increase the delay.