Enhanced analogue front-end for the measurement of the high state of wide-band voltage pulses with 87 dB common-mode rejection ratio and ±0.65 ppm 1-day offset stability

The proof of principle of an on-line digitizer designed to be integrated into the digital control loop of a high-voltage modulator for ultra-repeatable power converters is presented. The presented selective analogue zoom allows digitizing with ±18 ppm repeatability the voltage around the nominal level (10 V±1 V) and, at the same time, the initial transients with relaxed performance. In addition, in order not to jeopardize the digital control loop stability, the whole digitizing system has to introduce a low real-time delay; this is assessed to be less than 1.2 µs. Initially, the specifications of the real-time control are presented and translated into data acquisition requirements. Then, the main design choices of the digitizer are discussed and Pspice simulation results are reported to validate the concept design. Finally, experimental results of a validation case study developed for the power converter designed at ET H Zurich and University of Laval for the new linear particle accelerator under study at CE RN, the Compact LInear Collider CLIC, are reported and compared with the simulation outcomes.

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“…On the lower branch in figure 8 (violet dashed rectangle), a differential sensing circuit is used on the signal input in order to [20,24]:…”

Section: Input Stage (Signal)mentioning

confidence: 99%

“…The test setup of figure 20a, already used in [24], allows CM RR ref to be assessed over a frequency range of 1 MHz. In this test, the AC common-mode voltage was imposed between the references of two DC generators.…”

Section: Ac Cmrrmentioning

confidence: 99%

Proof of principle of an on-line digitizer with ±18 ppm repeatability and 1.2 μs real-time delay for power converters control loop

et al. 2017

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Design of a real-time acquisition system for the CLIC klystron modulators control loop

Arpaïa

Baccigalupi

Bastos

et al. 2016

2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings

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The proof of principle of a real-time data acquisition system to be integrated into a digital control loop for controlling the power converters of the Compact LInear Collider is presented. The system is based on an ultra low noise analogue front-end with 1:1 ppm RMS noise (referred to input), and about 1 _s of real-time delay. After the analogue conditioning, a fully-differential analogue-todigital converter is foreseen. The requirements of this system, directly derived from the accelerator performance, are discussed and translated into design specification. The results obtained by means of Pspice simulations are reported in order to prove that the design is feasible with the proposed architecture. Finally, the results of the experimental validation of the prototype, currently under design, will be included in the final paper. Real-Time Acquisition System Fig. 1. Basic Diagram of a Control SystemAbstract -The proof of principle of a real-time data acquisition system to be integrated into a digital control loop for controlling the power converters of the Compact LInear Collider is presented. The system is based on an ultra low noise analogue front-end with 1.1 ppm RM S noise (referred to input), and about 1 µs of real-time delay. After the analogue conditioning, a fully-differential analogue-todigital converter is foreseen. The requirements of this system, directly derived from the accelerator performance, are discussed and translated into design specification. The results obtained by means of Pspice simulations are reported in order to prove that the design is feasible with the proposed architecture. Finally, the results of the experimental validation of the prototype, currently under design, will be included in the final paper.

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Enhanced analogue front-end for the measurement of the high state of wide-band voltage pulses with 87 dB common-mode rejection ratio and ±0.65 ppm 1-day offset stability

Cited by 2 publications

References 13 publications

Proof of principle of an on-line digitizer with ±18 ppm repeatability and 1.2 μs real-time delay for power converters control loop

Proof of principle of an on-line digitizer with ±18 ppm repeatability and 1.2 μs real-time delay for power converters control loop

Design of a real-time acquisition system for the CLIC klystron modulators control loop

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