Engineering the cascoded NMOS output buffer for maximum V/sub t1/

Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress

“…Section 3.2 has introduced that it is possible to observe some holes in gates of cascoded protection devices induced by MM stress (like CDM signature) [6][7][8]. A 2D simulation is performed to try to confirm this observation.…”

Latchup in voltage tolerant circuits: a new phenomenon

“…The placement of D1 with respect to the cascode NMOS transistors M1/M2 is critical to the ESD operation. The parasitic pnp built into D1 is being used to pump the local substrate in order to turn on the composite parasitic NPN formed between the drain of M1 and the source of M2 [9][10][11][12]. Note that this effective NPN triggers when the cascoded devices are integrated in layout.…”

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

“…However, the nMOS in stacked configuration has a higher trigger voltage and a higher snapback holding voltage , but a lower secondary breakdown current , as compared to the single nMOS [19]. Therefore, such mixed-voltage I/O circuits with stacked nMOS often have much lower ESD levels under the positive-to-ESD stress condition, as compared to the I/O circuits with a single nMOS [19], [20].…”