Engineering strained silicon on insulator wafers with the Smart CutTM technology

Ghyselen, B.; Hartmann, Jean‐Michel; Ernst, T.; Aulnette, C.; Osternaud, B.; Bogumilowicz, Y.; Abbadie, A.; Besson, P.; Rayssac, O.; Tiberj, Antoine; Daval, N.; Cayrefourq, I.; Fournel, Frank; Moriceau, H.; Nardo, C. Di; Andrieu, F.; Paillard, Vincent; Cabié, Martiane; Vincent, L.; Snoeck, E.; Cristiano, F.; Rocher, A.; Ponchet, Anne; Claverie, A.; Boucaud, P.; Séméria, M. N.; Bensahel, D.; Kernevez, N.; Mazuré, C.

doi:10.1016/j.sse.2004.01.011

Cited by 117 publications

(54 citation statements)

References 21 publications

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“…5 X-ray diffraction analysis confirmed the good crystalline quality and a relaxation degree of about 95%-98% of the layers. Dislocation densities measured by wet chemical revelation are typically in the 10 4 cm −2 range.…”

Section: Methodsmentioning

confidence: 67%

“…2-4 The fabrication of s-SOI wafers using the Smart Cut™ technology has been demonstrated. [5][6][7][8] To fabricate such wafers, a layer detachment must occur in the SiGe film, which has served as a template for growing s-Si by epitaxy. We reported the studies of splitting kinetics involved H implantation into SiGe layers with different Ge concentrations.…”

Section: Introductionmentioning

confidence: 99%

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Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Nguyen

Bourdelle

Aulnette

et al. 2008

Journal of Applied Physics

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We have performed systematic measurements of the splitting kinetics induced by H-only and He + H sequential ion implantation into relaxed Si 0.8 Ge 0.2 layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si 0.8 Ge 0.2 . Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si 0.8 Ge 0.2 than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.

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Section: Methodsmentioning

confidence: 67%

Section: Introductionmentioning

confidence: 99%

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Nguyen

Bourdelle

Aulnette

et al. 2008

Journal of Applied Physics

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“…Global strain techniques are not restricted to bulk-CMOS technology and may be integrated into silicon-on-insulator wafers by layer transfer and wafer bonding techniques. Benefits of performance for n-channel MOSFETs with ultra-thin strained silicon on SiGe-on-insulator substrate (11,12) or strained silicon directly on insulator were successfully demonstrated with current drive enhancements of 20-25% reported (13,14).…”

Section: Strain Engineering Techniquesmentioning

confidence: 99%

“…Splitting of unprimed subbands Substituting [11] into the right-hand side of [10] and solving [10] for small strain one obtains the following dispersion relation for the unprimed subbands n:…”

Section: Subband Structure In Thick Filmsmentioning

confidence: 99%

Modeling Techniques for Strained CMOS Technology

et al. 2009

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We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22nm technology node and beyond. IntroductionThe rapid increase in computational power and speed of integrated circuits is supported by the aggressive size reduction of semiconductor devices. Downscaling of MOSFETs as institutionalized by Moore's law is successfully continuing because of innovative changes in the technological processes and the introduction of new materials. Until recently, the main method of increasing complementary metal-oxide semiconductors (CMOS) transistor performance was based on geometrical scaling, which has led to an enormous success in increasing the speed and functionality of electronic devices. Although a possibility to build a MOSFET with a gate length as short as 6nm has been demonstrated (1), the semiconductor industry is facing critical challenges with ongoing scaling. Among them are the short channel effects and the high power dissipation for small transistors, and the high gate leakage current for very thin gate dielectrics. Already now, for an oxide thickness of approximately 1.5nm, gate leakage makes it difficult to maintain a sufficiently high I on /I off ratio, which does not degrade MOSFET performance. Rising costs of chip manufacturing are making further scaling increasingly more difficult: the feasibility of fabrication cannot be easily guaranteed, and maintaining performance and reliability becomes a severe issue. With scaling apparently approaching its fundamental limits, the semiconductor industry is facing critical challenges. New engineering solutions and innovative techniques are required to improve CMOS device performance. Strain-induced mobility enhancement is the most attractive way to increase the device speed and will certainly take a key position among other technological changes for the next technology generations. The 32nm MOSFET process technology recently developed by Intel (2) employs advanced third generation strain engineering techniques. Apart from strain, the 32nm MOSFET process technology involves new hafnium-based high-k dielectric/metal gates first introduced for the 45nm technology node (3), which represented a major change in the technological process since the invention of MOSFETs. Although alternative chan...

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“…Silicon lines were etched from a (001) oriented sSOI substrate made by a wafer bonding technique from the Si deposition on a SiGe virtual substrate imposing a biaxial strain, as described in [19]. Lines in tensile strain ( yy = +0.78%) are oriented along the [110] direction which corresponds to the usual direction of n-MOSFET channels for which electron transport is improved.…”

mentioning

confidence: 99%

Time-Dependent Relaxation of Strained Silicon-on-Insulator Lines Using a Partially Coherent X-Ray Nanobeam

et al. 2013

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We report on the quantitative determination of the strain map in a strained Silicon-On-Insulator (sSOI) line with a 200 × 70 nm 2 cross-section. In order to study a single line as a function of time, we used an X-ray nanobeam with relaxed coherence properties as a compromise between beam size, coherence and intensity. We demonstrate how it is possible to reconstruct the line deformation at the nanoscale, and follow its evolution as the line relaxes under the influence of the X-ray nanobeam.PACS numbers: 41.50.+h, 68.60.Bs New applications in optoelectronic and electronic semiconductor devices have been achieved by a careful control of strain at the nanoscale level. Several physical properties such as charge carrier mobility in transistors and emission wavelength in quantum dots or well heterostructure have been advantageously improved by applying strain fields adapted to the materials band structure, orientation and doping features [1][2][3][4].The measurement of these strain fields has required the development of dedicated techniques with adapted spatial and strain resolution. Electronic imaging techniques have seen tremendous developments and outstanding achievements [5], but are always limited by the preparation of thin foil that can considerably relieve internal stress in nanostructures. Very recently, X-ray diffraction has taken profit of the highly brilliant and coherent radiation provided by synchrotron sources [6]. Moreover, the optimization of dedicated focusing optics (compound refractive lenses [7], Fresnel Zone Plate (FZP) [8,9], Kirkpatrick-Baez mirrors [10,11]) has allowed the use of nanobeams, increasing the spatial resolution of diffraction measurements. This also allowed the use of coherent X-ray diffraction imaging (CXDI) for structure (shape, size) and strain determination of single nano-objects [12][13][14][15][16].In this letter, we illustrate how the strain of a single strained silicon nanostructure changes during irradiation with x-rays, as a function of measurement time using a partially coherent X-ray nanobeam. Strained SiliconOn-Insulator (sSOI) lines are considered due to their strong interest for enhancing the carrier mobility in metal oxide semiconductors field-effect-transistors (MOSFET) devices [17,18].Silicon lines were etched from a (001) oriented sSOI substrate made by a wafer bonding technique from the Si deposition on a SiGe virtual substrate imposing a biaxial strain, as described in [19]. Lines in tensile strain ( yy = +0.78%) are oriented along the [110] direction which corresponds to the usual direction of n-MOSFET channels for which electron transport is improved. The strain relaxes elastically along [110], i.e. perpendicularly to the lines [18]. An in-plane misorientation of about 1 o is used between the strained Si lines and the Si substrate in order to separate the line and substrate Bragg peaks. The sSOI lines have a width W=225 nm and a height H=70 nm (Fig. 1) and lie on a 145 nm SiO 2 layer. The distance d between two adjacent lines is about 775 nm. Grazing-incid...

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Engineering strained silicon on insulator wafers with the Smart CutTM technology

Cited by 117 publications

References 21 publications

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Modeling Techniques for Strained CMOS Technology

Time-Dependent Relaxation of Strained Silicon-on-Insulator Lines Using a Partially Coherent X-Ray Nanobeam

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