Engineering of Grain Boundaries in CeO₂ Enabling Tailorable Resistive Switching Properties

Abstract

With their recent advances in memory and neuromorphic computing applications, resistive random-access memory (RRAM) emerges as one of the most promising electronic devices to change computational data management. The neuromorphic computing enabled by RRAMs provides viable solution to overcoming the limitations of the von-Neumann bottleneck for next-generation memory and computing applications. [1] As one type of RRAM, valence change memory made of oxides has numerous merits including large ON/OFF ratio, excellent endurance/retention, high switching speed, and simple fabrication. [2][3][4] Resistive switching (RS) in valence change memory is often realized by the change of electronic states of cations related to oxygen vacancies. Over the years, RS has been widely reported in many simple binary oxides (TiO 2 , [1,[5][6][7] HfO 2 , [8][9][10] CeO 2 , [11][12][13] and SiO 2 , [14,15] ) and ternary oxides Defect engineering in valence change memories aimed at tuning the concentration and transport of oxygen vacancies are studied extensively, however mostly focusing on contribution from individual extended defects such as single dislocations and grain boundaries. In this work, the impact of engineering large numbers of grain boundaries on resistive switching mechanisms and performances is investigated. Three different grain morphologies, that is, "random network," "columnar scaffold," and "island-like," are realized in CeO 2 thin films. The devices with the three grain morphologies demonstrate vastly different resistive switching behaviors. The best overall resistive switching performance is shown in the devices with "columnar scaffold" morphology, where the vertical grain boundaries extending through the film facilitate the generation of oxygen vacancies as well as their migration under external bias. The observation of both interfacial and filamentary switching modes only in the devices with a "columnar scaffold" morphology further confirms the contribution from grain boundaries. In contrast, the "random network" or "island-like" structures result in excessive or insufficient oxygen vacancy concentration migration paths. The research provides design guidelines for grain boundary engineering of oxide-based resistive switching materials to tune the resistive switching performances for memory and neuromorphic computing applications.

Self-Assembled Au Nanoelectrodes: Enabling Low-Threshold-Voltage HfO2-Based Artificial Neurons

“…A range of defect engineering methods and structural designs have been employed to enhance the performance of resistive switching materials toward neuromorphic computing. These methods include utilizing dislocations and grain boundaries as transport channels, − doping, − embedding metal nanoparticles, − and special patterning of the top or bottom electrodes. , Among these methods, embedding metal nanoparticles and utilizing patterned electrodes have been recognized as highly effective approaches to enhance the control of filament formation and reduce the switching voltage by manipulating the electric field distribution in the oxide switching layer. However, the fabrication process associated with both methods tends to be complex and costly.…”