Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance

Kansal, Harshit; Medury, Aditya Sankar

doi:10.1016/j.mejo.2023.105917

Cited by 1 publication

(2 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, when t FE is increased, the negative capacitance helps to increase the electron BTBT, thereby improving the electrical characteristics of NC-Ge-vTFET. In addition, it is also observed that due to the presence of both lateral and vertical BTBT in the device, the shift in the threshold voltage (V T ) is considerably greater for variation in t FE as compared to lateral tunneling NC TFET [38]. The enhancement in the electrical characteristic could well be clarified further from (2) and figure 3(b), in which the voltage drop across the ferroelectric film (V FE ) is increased with an increase in t FE , along with the total gate charge (Qg), offering an improved electrostatic coupling as well as better gate control over the channel.…”

Section: Impact Of Fe Film Thickness On Electrical Performancementioning

confidence: 99%

“…A BOX engineered NC FDSOI FET has also been proposed to minimize the NDR effect [37]. Furthermore, using a drain-side Paraelectric (PE) spacer, in addition to reduced drain doping, the NDR impact can also be lowered [38]. Recently, the NDR effects on tunnel FET have been investigated [39], however, the analysis is carried out only for lateral or point band-to-band tunneling TFET.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Vanlalawmpuia

2024

Phys. Scr.

View full text Add to dashboard Cite

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (tFE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher tFE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

show abstract

Section: Impact Of Fe Film Thickness On Electrical Performancementioning

confidence: 99%