Engineered Coalescence by Annealing 3D Ge Microstructures into High-Quality Suspended Layers on Si

Abstract

The move from dimensional to functional scaling in microelectronics has led to renewed interest toward integration of Ge on Si. In this work, simulation-driven experiments leading to high-quality suspended Ge films on Si pillars are reported. Starting from an array of micrometric Ge crystals, the film is obtained by exploiting their temperature-driven coalescence across nanometric gaps. The merging process is simulated by means of a suitable surface-diffusion model within a phase-field approach. The successful comparison between experimental and simulated data demonstrates that the morphological evolution is driven purely by the lowering of surface-curvature gradients. This allows for fine control over the final morphology to be attained. At fixed annealing time and temperature, perfectly merged films are obtained from Ge crystals grown at low temperature (450 °C), whereas some void regions still persist for crystals grown at higher temperature (500 °C) due to their different initial morphology. The latter condition, however, looks very promising for possible applications. Indeed, scanning tunneling electron microscopy and high-resolution transmission electron microscopy analyses show that, at least during the first stages of merging, the developing film is free from threading dislocations. The present findings, thus, introduce a promising path to integrate Ge layers on Si with a low dislocation density.

Dislocation-Free SiGe/Si Heterostructures

“…The suspended film displayed in Figure 6 was obtained [30] by prolongated high-temperature annealing of vertical Ge crystals on Si pillars. Temporal snapshots of the evolution are also displayed, together with a corresponding continuum simulation [31] (panel b).…”

“…First, local rounding of the facets occurs; then, connection bridges form between neighboring crystals leaving holes, that are finally filled by material flow. Reproduced with permission from[30]. American Chemical Society.…”

Integration of InGaP/GaAs/Ge triple-junction solar cells on deeply patterned silicon substrates

“…In the case of patterned substrates, the same growth conditions as for the UP ones were used; only the thickness of the Ge layer was increased to 8 µm in order to obtain complete coalescence of the Ge patches . Moreover, after the growth and the 6 annealing cycles between 600 and 800°C, the patterned samples underwent a further step of in situ steady annealing at 800°C for 1 h, in order to recover a nearly flat two‐dimensional Ge layer.…”

“…We deposited 4 µm of Ge in the case of planar substrates in order to ensure good absorption of sunlight in the Ge junction. The thickness was increased to 8 µm for patterned samples in order to ensure the complete coalescence of the Ge . Post‐growth cyclic thermal annealing from 600 to 800°C was performed in situ to promote dislocation motion, thus reducing their density in the Ge epilayer, in both patterned and UP samples .…”

“…The use of a high rate deposition technique at low growth temperature ensures a fairly low TD density , a very small surface roughness, and a kinetically limited three‐dimensional growth on the patterned substrates . The recovery of a continuous Ge layer across the etched trenches of the Si wafer was obtained by extended in situ steady annealing at 800°C ; this step was performed only on patterned samples.…”