Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Abstract

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions are far from realistic by evaluating losses and dispersion in commercial chips. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce losses by 47 dB and dispersion by 7.3×, enabling intrachip wireless communications over 10 Gb/s and only 1.9 dB away from the dispersion-free case.

Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics

“…Some works appeared in the 2007-2013 period, followed by a significant surge of papers from 2017 to date. Most efforts have been centered in the more mature bands between 20 GHz and 60 GHz [32], [54], [56], [59], [63], [69], [70], [73], with some forays into frequencies over 100 GHz [52], [55], [64], [79].…”

“…This is because the reverberation chamber model assumes full encasement and does not take dielectric losses into account, thus increasing the importance of the reflections. For flip-chip and custom packages, which fall in between these two extremes, the simulated delay spread has been of a few hundreds of picoseconds [35], [52] (see Figure 7 for a partial reproduction of data from [79]). In this context, it may not be possible to provide the speeds of several tens of Gb/s promised in several works [10], since the coherence bandwidth would be around a few GHz at most.…”

“…Therefore, waveguide-like and enclosed structures are equally crucial to minimize delay spread just as they are indispensable for path loss. Having this in mind, Timoneda et al proposed to optimize the flip-chip package taking dispersion into account [79]. For instance, it was shown that thinning down the silicon can have a positive effect on the delay spread, as shown in Figure 7.…”

Analysis of Near-Capacity Iterative Decoding Schemes for Wireless Communication Using EXIT Charts

“…Thanks to the breakthroughs in channel coding, it is feasible to design systems which are approaching Shannon's capacity and utilizing single transmitter and receiver [11][12][13]. Some important techniques of channel characterization, channel engineering and static transceiver optimization are discussed in [14] for enhancing the wireless propagation scenario.…”

Opportunistic Beamforming in Wireless Network-on-Chip

“…This paper proposes an opportunistic solution to this problem, seeking to implement spatial multiplexing in a flexible and affordable way for wireless on-chip networks. The main idea is to leverage the known channel characteristics [28], the already existing high density of on-chip antennas, and the already existing tight synchronization among cores to create small antenna arrays as shown in Fig. 1.…”