Energy-speed exploration for very-wide range of dynamic V-F scaling

Stangherlin, Kleber; Bampi, Sérgio

doi:10.1109/sbcci.2013.6644884

Cited by 4 publications

(1 citation statement)

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“…Circuits operating at near-or sub-VT result in extremely low and highly-variable performance, as shown in [11]. For applications like multimedia, which intrinsically allows a more relaxed accuracy operation [2], the key is to approximate the computations in order to recover performance and reduce power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance

Soares¹,

Bampi²,

Rosa

et al. 2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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Near-threshold computing in CMOS is a promising alternative for any application which can tolerate very wide voltage-frequency scaling (VFS). Internet-of-Things (IoT) devices will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT is the alternative we explore for VLSI circuits (8051 processor, filters, and ISCAS benchmark circuits). This paper proposes a method to design CMOS circuits for a wide dynamic range of VFS, and targets near-threshold for best efficiency. A standard-cell based design methodology specific for near-VT is demonstrated here in for a commercial 65nm CMOS process. Power and timing variability are characterized, so that variation-aware and yet ultra-low supply voltage designs are enabled. Our cell design method avoids unnecessary upsizing and it focus on near-and well above threshold regions of operation. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) we demonstrate 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each supply voltage. The extremely low and highly-variable performance at sub-and near-VT have to be addressed by new logic design paradigms. In this paper we also exploit the use of approximate adders to increase the timing performance of a class of digital filter circuits, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19.4% and 36.7% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our approximate adder method enables higher levels of energy efficiency in CMOS VLSI filters.

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Section: Introductionmentioning

confidence: 99%