Energy Optimization of Unrolled Block Ciphers Using Combinational Checkpointing

Dhanuskodi, Siva Nishok; Holcomb, Daniel

doi:10.1007/978-3-319-62024-4_4

Cited by 4 publications

(3 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The use of glitch filtering to reduce ASIC power has previously been explored [4,10,21]. For glitch filtering, ASICs provide a simpler platform than FPGAs since clock generation is more straightforward and delays can be tightly controlled.…”

Section: Glitches and Glitch Filteringmentioning

confidence: 99%

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays

Dumpala

Patil

Holcomb

et al. 2018

ACM Trans. Reconfigurable Technol. Syst.

Self Cite

View full text Add to dashboard Cite

Field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.

show abstract

Section: Glitches and Glitch Filteringmentioning

confidence: 99%

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays

Dumpala

Patil

Holcomb

et al. 2018

ACM Trans. Reconfigurable Technol. Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The technique proposed in [18] Combinational checkpointing proposed in [10] uses latch based glitch filters to reduce glitch propagation in unrolled block ciphers. This technique is targeted to application specific integrated circuits (ASICs) and cannot be directly applied to FP-GAs.…”

Section: Thesis Outlinementioning

confidence: 99%

“…We implemented glitch filtering on AES-256 and SIMON-128 block ciphers and a bitonic sort algorithm. Figure 3.1 [10] shows glitch filter approach for unrolled block ciphers. Figure 3.1: Unrolled block cipher with latch-based glitch filtering [10] The block cipher input is provided from a launch register from where it goes through one or more encryption rounds.…”

Section: Glitch Filter Operationmentioning

confidence: 99%