“…In CMOS designs, power consumption increases with clock frequency, and 100-GHz operation is impractical because of heat problems. On the contrary, the dynamic power needed for an SFQ logic gate which uses more energy-efficient technology, such as ERSFQ, is about 1/10,000 of that needed for a CMOS logic gate [26], e.g., 0.01 μW even at 100 GHz operation. Therefore, such a fine-grained pipeline structure is suitable for SFQ microprocessors.…”