Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications

Surana, Neelam; Mekie, Joycee

doi:10.1109/tcsii.2018.2869945

Cited by 45 publications

(13 citation statements)

References 12 publications

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“…For SRAM‐based memory, bit lines consume maximum power during the charging and discharging phase while performing the read and write operation 18 . To rectify the same, a single‐ended six‐transistor (6TSE) SRAM bit cell was reported by Surana and Mekie 19 in 2019 (Figure 1b). The memory core for 6TSE bit cell is composed of two inverter pairs (PR–NR) and (PL–NL), wherein NL is modified to always function in cutoff region.…”

Section: Schematic Review Of the Existing Sram Bit Cellsmentioning

confidence: 99%

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Rawat

Mittal

2021

Circuit Theory & Apps

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Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.

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Section: Schematic Review Of the Existing Sram Bit Cellsmentioning

confidence: 99%

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Rawat

Mittal

2021

Circuit Theory & Apps

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“…The SRAM is used to store local data when a gateway is not available for communication. This cell is widely distributed in the modern application and occupies a large portion of System-onchip [1]. In SRAM cell, power dissipation becomes the prominent factor in the rising demand for Internet of Things (IoT) based portable devices.…”

Section: Introductionmentioning

confidence: 99%

“…In 6T SRAM cell, differential bit-line structure increases read and write power dissipation as of single-ended 6T SRAM cell [1]. Single ended SRAM topologies [1,16,[22][23][24] are reported to reduce the power dissipation during read/write operation. P.Singh et al [18] proposed a positive feedback-controlled (PCF10T) SRAM cell with a single ended read operation.…”

Section: Introductionmentioning

confidence: 99%

“…In IoT based devices, there is a crucial demand for low power devices which can support long-term operation with extend battery life. In 6T SRAM cell, differential bit-line structure increases read and write power dissipation as of single-ended 6T SRAM cell [1]. Single ended SRAM topologies [1,16,[22][23][24] are reported to reduce the power dissipation during read/write operation.…”

Section: Introductionmentioning

confidence: 99%

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A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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“…Multimedia applications are inherently error tolerant where errors can be tolerated in lower order bits (LOBs) of a pixel. This fact is exploited in [3–5, 7–12] to design low power SRAM architecture for H.264 video decoder

normalPSNR = 20 \times \log_{10} \frac{255}{\sqrt{MSE}},

normalMSE = \frac{1}{M N} {false\sum}_{i = 0}^{M - 1} {false\sum}_{j = 0}^{N - 1} [I (i, j) - I_{normalref} (i, j)]^{2},

Peak‐signal‐to‐noise ratio (PSNR) gives the quantitative measure of the relative quality of an image/video with respect to the original error‐free image/video [7] which is defined in (1) and (2), where, MSE is the mean square error calculated based on pixel differences between images stored in approximate and exact memories.…”

Section: Introductionmentioning

confidence: 99%

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Bharti

Surana

Mekie

2019

IET Computers & Digital Techniques

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Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications

Cited by 45 publications

References 12 publications

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

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