Energy-efficient scheduling of streaming applications in VFI-NoC-HMPSoC based edge devices

Tariq, Umair Ullah; Ali, Haider; Liu, Lu; Hardy, Jennifer

doi:10.1007/s12652-020-02749-7

Cited by 5 publications

(2 citation statements)

References 46 publications

(55 reference statements)

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“…Tariq et al [24] have experimented real-time streaming application scheduling on edge devices while taking energy considerations into account. To begin with, a cutting-edge retiming-based technique was created to convert the dependent workload into an independent task model in order to free up resources and the processors' unused slack with a potential minimal preamble.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The maximum execution time of the cores in the VFI is determined by constraint (23). In order to prevent exceptionally uneven VFI sizes that raise the benchmark's execution time or system energy consumption, constraint (24) mandates that each VFI have a minimal number of cores. The core c i is contained in a single VFI i k by constraint (25).…”

Section: G Vfi Partitioningmentioning

confidence: 99%

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Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Sanchit

Singh

2023

IEEE Access

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Scheduling a Directed Acyclic Graph (DAG) on voltage frequency islands involves dividing the available processing units into multiple islands with varying voltage and frequency levels, and then mapping the tasks of the DAG to the islands while minimizing the makespan and overall energy consumption. In this research work, a novel DAG task scheduling model is introduced with the assistance acquired from the deep learning paradigm. The proposed model includes four major phases: (a) DAG modelling, (b) Voltage frequency island partitioning, (c) core temperature prediction and (d) scheduling optimization. Initially, the Directed Acyclic Graph (DAG) model is designed. The nodes of DAG represent tasks and the edges represent dependencies between tasks. Then, in the Voltage frequency island partitioning, the available processing units into multiple voltage frequency islands. This can be done based on the power consumption of each unit, and the task requirements. Subsequently, the Recurrent Neural Network (RERNN) is trained to predict the core temperature of each voltage frequency island based on the multi-objectives like execution time, makespan, overall energy consumption. Then, the scheduling of the DAG on the voltage frequency islands is optimized using the Self-Improved Pelican Optimization Algorithm (SI-POA). The proposed SI-POA model is an extended version of the standard POA model. The SI-POA model is inspired by the behavior by the natural behavior of pelicans during hunting. In the scheduling optimization phase, the SI-POA algorithm to optimize the scheduling of the DAG on the voltage frequency islands while taking into account the predicted core temperature of each island based on the Recalling-enhanced recurrent neural network (RERNN) model. The goal is to minimize the makespan and overall energy consumption of the DAG while keeping the core temperature of each island within safe limits.

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Section: Literature Reviewmentioning

confidence: 99%

Section: G Vfi Partitioningmentioning

confidence: 99%

Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Sanchit

Singh

2023

IEEE Access

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Allocating energy-objective aware workflow in distributed edge micro data centres

Kadum,

Deng

2023

J Supercomput

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A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms

Saleem,

Hussain,

Amin

et al. 2023

IEEE Access

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Network-on-Chip (NoC) has been unfolded as a superior alternative for integrating a considerably greater extent of cores on a single chip. Recently, multi-core systems have become prevalent because of the increased processing demands for high-performance embedded applications. Application mapping techniques play a significant role in enhancing the extensive performance of such complex multicore platforms. Developing and implementing efficient application mapping techniques are required for system design to meet the demand of such complicated multi-core systems. The paper primarily focuses on dynamic application mapping techniques, classifying them into a number of subcategories. It highlights such approaches and techniques that aim to enhance the performance of the NoC-based systems by optimizing them in terms of communication cost, latency, energy consumption, power, execution, and computational time. Future challenges, trends, and simulation tools have also been spotlighted. INDEX TERMSNetwork-on-Chip, Application mapping, System-on-Chip, VOPD.I. INTRODUCTION D UE to the rise in complexity of embedded This is some system devices, system-on-chip (SoC) incorporating the numerous processing cores on a single chip to perform various functions is the primary paradigm of today's digital world. The SoC uses a shared medium bus to communicate intellectual property (IP) cores and is widely utilized in domain-specific devices [1], [2], such as aerospace, medical sciences, microprocessors-based technology, and wireless communications. Due to the higher density of components in SoC, the implementation of a shared-bus architecture is getting complicated. As the number of cores increases on the chip, the performance is not enhanced and scaled by the increased processing cores due to the limitations of the shared-bus architecture. Network-on-chip (NoC) has emerged as a feasible substitute to cater to the new inter-core communication demands of the growing number of 17 components on a chip and faster communication between 18 the cores [3]. NoC architecture is considered a part of or 19 a subset of SoC-based technology [4]. NoC uses IP cores 20 connected with the routers and inter-switch links [5], and 21 the communication between the cores is done by transferring 22 packets with these routers and links. Messages are divided 23 into smaller packets to be transmitted between various cores 24 that allow for the efficient use of network resources. NoC 25 employs a routing algorithm for the determination of the 26 path that each packet follows from the source to the destina-27 tion. Various switching techniques are developed to transfer 28 packets such as circuit and packet switching. A physical 29 path from source to destination is reserved before the data 30 transmission in circuit switching. While in packet switching, 31 each message is partitioned into fixed-length packets which 32

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Energy-efficient scheduling of streaming applications in VFI-NoC-HMPSoC based edge devices

Cited by 5 publications

References 46 publications

Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Allocating energy-objective aware workflow in distributed edge micro data centres

A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms

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