Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kuan, Kyle; Adegbija, Tosiron

doi:10.1109/tcad.2019.2912920

Cited by 20 publications

(25 citation statements)

References 33 publications

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“…These methods of solve the asymmetry of NVM are very valuable. There are also a lot of works [8,9,10,11,12,18,19,20,21,22] focusing on the research of STT-RAM-based cache. Komalan [22] obtains a smaller on-chip area and lower energy by adding a buffer between the CPU and L1 D-cache at the expense of 8% performance loss.…”

Section: Related Workmentioning

confidence: 99%

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Chen

Hao

et al. 2022

IEICE Electron. Express

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Large-sized cache is beneficial to improve CPU performance especially for IoT applications with huge amount of data. However, largesized SRAM cache also increases chip area and energy which is not friendly to resources limited IoT terminals. The STT-RAM with high storage density and near zero leakage is regarded as an ideal technology to replace SRAM. Prefetching is a vital method to hide the access latency of off-chip memory. Nevertheless, traditional prefetchers for SRAM is inadequate for MRAM cache with read-write asymmetry. Aggressive prefetching for STT-RAM cache would cause cache congestion and dynamic energy rise because of STT-RAM long write latency and high write energy. In response to the above problems, this paper novelty proposes WANCP (Write-awareness Adaptive Non-volatile Cache Prefetch), which adaptively adjusts the prefetch aggressiveness according to the saturation of MSHR (Miss-status Handling Registers) in the L2 cache. Experiments show that, for applications that are sensitive to L2 cache capacity, the CPU performance with STT-RAM L2 cache can be improved by up to 33.2% and 10.9 % on average compared to the same sized SRAM L2 cache. The proposed WANCP can further improve the CPU performance 0.4 % on average, and reduce the prefetch energy by 9.4% on average.

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Section: Related Workmentioning

confidence: 99%

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Chen

Hao

et al. 2022

IEICE Electron. Express

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“…Several prior studies tried to enhance the performance of STT-RAM in order to use it for building a large cache [2,[30][31][32][33][34][35][36][37]. In [30][31][32], and the retention time of STT-RAM is reduced to mitigate the long write latency of STT-RAM.…”

Section: Related Workmentioning

confidence: 99%

“…Chi et al [2] introduced state-of-the-art architectural approaches to adopt STT-RAM in the cache. Kuan et al [34,35] proposed an STT-RAM-based cache that allows LLC configurations and retention time to be adapted to applications' runtime execution requirements.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Kim

Nair

et al. 2022

Electronics

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STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

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“…For a multicore environment, applying cache partitioning with an HCA has been studied [14][15] [16]. In addition to the last-level cache, the L1 cache is also becoming a target of HCAs [17] [18]. Another approach for HCA is mixing DRAM and NVM…”

Section: Introductionmentioning

confidence: 99%

Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture

Choi

Park

2021

IEICE Electron. Express

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A hybrid cache architecture (HCA) is introduced to alleviate the drawbacks of non-volatile memory (NVM) technologies. Although researchers have offered meaningful ways to conserve energy, little attention has been paid to focus on write counts that are non-uniformly spread over a cache line. We propose a novel HCA to reduce the NVM write counts by exploiting bit-level write patterns. The data array is refined to separately store bits in the cache line to the NVM region and the SRAM region. As a result, 20.1% of energy is saved over prior works.

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Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Cited by 20 publications

References 33 publications

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture

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